mirror of https://github.com/xemu-project/xemu.git
i386: move TCG cpu class initialization to tcg/
to do this, we need to take code out of cpu.c and helper.c, and also move some prototypes from cpu.h, for code that is needed in tcg/xxx_helper.c, and which in turn is part of the callbacks registered by the class initialization. Therefore, do some shuffling of the parts of cpu.h that are only relevant for tcg/, and put them in tcg/helper-tcg.h For FT0 and similar macros, put them in tcg/fpu-helper.c since they are used only there. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-8-cfontana@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
parent
40399ecb69
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ed69e8314d
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@ -24,6 +24,8 @@
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "tcg/tcg-cpu.h"
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#include "tcg/helper-tcg.h"
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#include "exec/exec-all.h"
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#include "sysemu/kvm.h"
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#include "sysemu/reset.h"
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@ -1521,7 +1523,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
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cpu->env.features[FEAT_XSAVE_COMP_LO];
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}
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const char *get_register_name_32(unsigned int reg)
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/* Return name of 32-bit register, from a R_* constant */
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static const char *get_register_name_32(unsigned int reg)
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{
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if (reg >= CPU_NB_REGS32) {
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return NULL;
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@ -7068,13 +7071,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
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cpu->env.eip = value;
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}
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static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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X86CPU *cpu = X86_CPU(cs);
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cpu->env.eip = tb->pc - tb->cs_base;
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}
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int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
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{
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X86CPU *cpu = X86_CPU(cs);
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@ -7309,17 +7305,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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cc->class_by_name = x86_cpu_class_by_name;
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cc->parse_features = x86_cpu_parse_featurestr;
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cc->has_work = x86_cpu_has_work;
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#ifdef CONFIG_TCG
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cc->do_interrupt = x86_cpu_do_interrupt;
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cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
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#endif
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tcg_cpu_common_class_init(cc);
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#endif /* CONFIG_TCG */
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cc->dump_state = x86_cpu_dump_state;
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cc->set_pc = x86_cpu_set_pc;
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cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
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cc->gdb_read_register = x86_cpu_gdb_read_register;
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cc->gdb_write_register = x86_cpu_gdb_write_register;
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cc->get_arch_id = x86_cpu_get_arch_id;
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cc->get_paging_enabled = x86_cpu_get_paging_enabled;
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#ifndef CONFIG_USER_ONLY
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cc->asidx_from_attrs = x86_asidx_from_attrs;
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cc->get_memory_mapping = x86_cpu_get_memory_mapping;
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@ -7330,7 +7327,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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cc->write_elf32_note = x86_cpu_write_elf32_note;
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cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
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cc->vmsd = &vmstate_x86_cpu;
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#endif
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#endif /* !CONFIG_USER_ONLY */
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cc->gdb_arch_name = x86_gdb_arch_name;
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#ifdef TARGET_X86_64
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cc->gdb_core_xml_file = "i386-64bit.xml";
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@ -7338,15 +7336,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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#else
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cc->gdb_core_xml_file = "i386-32bit.xml";
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cc->gdb_num_core_regs = 50;
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#endif
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#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
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cc->debug_excp_handler = breakpoint_handler;
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#endif
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cc->cpu_exec_enter = x86_cpu_exec_enter;
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cc->cpu_exec_exit = x86_cpu_exec_exit;
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#ifdef CONFIG_TCG
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cc->tcg_initialize = tcg_x86_init;
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cc->tlb_fill = x86_cpu_tlb_fill;
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#endif
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cc->disas_set_info = x86_disas_set_info;
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@ -31,9 +31,6 @@
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#define KVM_HAVE_MCE_INJECTION 1
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/* Maximum instruction code size */
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#define TARGET_MAX_INSN_SIZE 16
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/* support for self modifying code even if the modified instruction is
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close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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@ -1775,12 +1772,6 @@ struct X86CPU {
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extern VMStateDescription vmstate_x86_cpu;
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#endif
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/**
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* x86_cpu_do_interrupt:
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* @cpu: vCPU the interrupt is to be handled by.
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*/
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void x86_cpu_do_interrupt(CPUState *cpu);
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bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
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int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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@ -1803,9 +1794,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void x86_cpu_exec_enter(CPUState *cpu);
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void x86_cpu_exec_exit(CPUState *cpu);
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void x86_cpu_list(void);
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int cpu_x86_support_mca_broadcast(CPUX86State *env);
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@ -1930,9 +1918,6 @@ void host_cpuid(uint32_t function, uint32_t count,
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void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
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/* helper.c */
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bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
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#ifndef CONFIG_USER_ONLY
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@ -1957,8 +1942,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
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void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
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#endif
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void breakpoint_handler(CPUState *cs);
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/* will be suppressed */
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
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@ -1968,16 +1951,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
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/* hw/pc.c */
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uint64_t cpu_get_tsc(CPUX86State *env);
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/* XXX: This value should match the one returned by CPUID
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* and in exec.c */
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# if defined(TARGET_X86_64)
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# define TCG_PHYS_ADDR_BITS 40
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# else
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# define TCG_PHYS_ADDR_BITS 36
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# endif
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#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
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#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
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#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_X86_CPU
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@ -2014,25 +1987,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
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#define CC_SRC2 (env->cc_src2)
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#define CC_OP (env->cc_op)
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/* n must be a constant to be efficient */
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static inline target_long lshift(target_long x, int n)
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{
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if (n >= 0) {
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return x << n;
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} else {
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return x >> (-n);
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}
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}
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/* float macros */
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#define FT0 (env->ft0)
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#define ST0 (env->fpregs[env->fpstt].d)
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#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
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#define ST1 ST(1)
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/* translate.c */
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void tcg_x86_init(void);
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typedef CPUX86State CPUArchState;
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typedef X86CPU ArchCPU;
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@ -2062,19 +2016,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
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uint64_t status, uint64_t mcg_status, uint64_t addr,
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uint64_t misc, int flags);
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/* excp_helper.c */
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void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
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void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
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uintptr_t retaddr);
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void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
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int error_code);
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void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
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int error_code, uintptr_t retaddr);
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void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
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int error_code, int next_eip_addend);
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/* cc_helper.c */
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extern const uint8_t parity_table[256];
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uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
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static inline uint32_t cpu_compute_eflags(CPUX86State *env)
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@ -2086,18 +2027,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
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return eflags;
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}
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/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
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* after generating a call to a helper that uses this.
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*/
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static inline void cpu_load_eflags(CPUX86State *env, int eflags,
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int update_mask)
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{
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CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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CC_OP = CC_OP_EFLAGS;
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env->df = 1 - (2 * ((eflags >> 10) & 1));
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env->eflags = (env->eflags & ~update_mask) |
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(eflags & update_mask) | 0x2;
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}
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/* load efer and update the corresponding hflags. XXX: do consistency
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checks with cpuid bits? */
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/* svm_helper.c */
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void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
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uint64_t param, uintptr_t retaddr);
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void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
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uint64_t exit_info_1, uintptr_t retaddr);
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void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
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/* seg_helper.c */
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void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
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/* smm_helper.c */
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void do_smm_enter(X86CPU *cpu);
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/* apic.c */
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void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
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void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
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*/
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void x86_cpu_set_default_version(X86CPUVersion version);
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/* Return name of 32-bit register, from a R_* constant */
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const char *get_register_name_32(unsigned int reg);
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void enable_compat_apic_id_mode(void);
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#define APIC_DEFAULT_ADDRESS 0xfee00000
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#define APIC_SPACE_SIZE 0x100000
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@ -24,10 +24,8 @@
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#include "sysemu/runstate.h"
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#include "kvm/kvm_i386.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/tcg.h"
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#include "sysemu/hw_accel.h"
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#include "monitor/monitor.h"
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#include "hw/i386/apic_internal.h"
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#endif
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void cpu_sync_bndcs_hflags(CPUX86State *env)
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@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu)
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}
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#endif
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/* Frob eflags into and out of the CPU temporary format. */
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void x86_cpu_exec_enter(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->df = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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}
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void x86_cpu_exec_exit(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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env->eflags = cpu_compute_eflags(env);
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}
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#ifndef CONFIG_USER_ONLY
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uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
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{
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@ -21,6 +21,7 @@
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "helper-tcg.h"
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#ifndef CONFIG_USER_ONLY
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@ -20,6 +20,7 @@
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "helper-tcg.h"
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const uint8_t parity_table[256] = {
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CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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@ -23,6 +23,7 @@
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#include "qemu/log.h"
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#include "sysemu/runstate.h"
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#include "exec/helper-proto.h"
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#include "helper-tcg.h"
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void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
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{
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@ -26,11 +26,18 @@
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#include "exec/cpu_ldst.h"
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#include "fpu/softfloat.h"
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#include "fpu/softfloat-macros.h"
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#include "helper-tcg.h"
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#ifdef CONFIG_SOFTMMU
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#include "hw/irq.h"
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#endif
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/* float macros */
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#define FT0 (env->ft0)
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#define ST0 (env->fpregs[env->fpstt].d)
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#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
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#define ST1 ST(1)
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#define FPU_RC_MASK 0xc00
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#define FPU_RC_NEAR 0x000
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#define FPU_RC_DOWN 0x400
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@ -2986,23 +2993,21 @@ void update_mxcsr_status(CPUX86State *env)
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void update_mxcsr_from_sse_status(CPUX86State *env)
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{
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if (tcg_enabled()) {
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uint8_t flags = get_float_exception_flags(&env->sse_status);
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/*
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* The MXCSR denormal flag has opposite semantics to
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* float_flag_input_denormal (the softfloat code sets that flag
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* only when flushing input denormals to zero, but SSE sets it
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* only when not flushing them to zero), so is not converted
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* here.
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*/
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env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
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(flags & float_flag_divbyzero ? FPUS_ZE : 0) |
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(flags & float_flag_overflow ? FPUS_OE : 0) |
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(flags & float_flag_underflow ? FPUS_UE : 0) |
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(flags & float_flag_inexact ? FPUS_PE : 0) |
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(flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
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0));
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}
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uint8_t flags = get_float_exception_flags(&env->sse_status);
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/*
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* The MXCSR denormal flag has opposite semantics to
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* float_flag_input_denormal (the softfloat code sets that flag
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* only when flushing input denormals to zero, but SSE sets it
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* only when not flushing them to zero), so is not converted
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* here.
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*/
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env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
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(flags & float_flag_divbyzero ? FPUS_ZE : 0) |
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(flags & float_flag_overflow ? FPUS_OE : 0) |
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(flags & float_flag_underflow ? FPUS_UE : 0) |
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(flags & float_flag_inexact ? FPUS_PE : 0) |
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(flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
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0));
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}
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void helper_update_mxcsr(CPUX86State *env)
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@ -0,0 +1,106 @@
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/*
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* TCG specific prototypes for helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
|
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef I386_HELPER_TCG_H
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#define I386_HELPER_TCG_H
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|
||||
#include "exec/exec-all.h"
|
||||
|
||||
/* Maximum instruction code size */
|
||||
#define TARGET_MAX_INSN_SIZE 16
|
||||
|
||||
/*
|
||||
* XXX: This value should match the one returned by CPUID
|
||||
* and in exec.c
|
||||
*/
|
||||
# if defined(TARGET_X86_64)
|
||||
# define TCG_PHYS_ADDR_BITS 40
|
||||
# else
|
||||
# define TCG_PHYS_ADDR_BITS 36
|
||||
# endif
|
||||
|
||||
#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
|
||||
|
||||
/**
|
||||
* x86_cpu_do_interrupt:
|
||||
* @cpu: vCPU the interrupt is to be handled by.
|
||||
*/
|
||||
void x86_cpu_do_interrupt(CPUState *cpu);
|
||||
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
|
||||
|
||||
/* helper.c */
|
||||
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||
MMUAccessType access_type, int mmu_idx,
|
||||
bool probe, uintptr_t retaddr);
|
||||
|
||||
void breakpoint_handler(CPUState *cs);
|
||||
|
||||
/* n must be a constant to be efficient */
|
||||
static inline target_long lshift(target_long x, int n)
|
||||
{
|
||||
if (n >= 0) {
|
||||
return x << n;
|
||||
} else {
|
||||
return x >> (-n);
|
||||
}
|
||||
}
|
||||
|
||||
/* translate.c */
|
||||
void tcg_x86_init(void);
|
||||
|
||||
/* excp_helper.c */
|
||||
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
|
||||
void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
|
||||
uintptr_t retaddr);
|
||||
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
|
||||
int error_code);
|
||||
void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
|
||||
int error_code, uintptr_t retaddr);
|
||||
void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
|
||||
int error_code, int next_eip_addend);
|
||||
|
||||
/* cc_helper.c */
|
||||
extern const uint8_t parity_table[256];
|
||||
|
||||
/*
|
||||
* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
|
||||
* after generating a call to a helper that uses this.
|
||||
*/
|
||||
static inline void cpu_load_eflags(CPUX86State *env, int eflags,
|
||||
int update_mask)
|
||||
{
|
||||
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
||||
CC_OP = CC_OP_EFLAGS;
|
||||
env->df = 1 - (2 * ((eflags >> 10) & 1));
|
||||
env->eflags = (env->eflags & ~update_mask) |
|
||||
(eflags & update_mask) | 0x2;
|
||||
}
|
||||
|
||||
/* svm_helper.c */
|
||||
void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
|
||||
uint64_t exit_info_1, uintptr_t retaddr);
|
||||
void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
|
||||
|
||||
/* seg_helper.c */
|
||||
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
|
||||
|
||||
/* smm_helper.c */
|
||||
void do_smm_enter(X86CPU *cpu);
|
||||
|
||||
#endif /* I386_HELPER_TCG_H */
|
|
@ -24,6 +24,7 @@
|
|||
#include "exec/helper-proto.h"
|
||||
#include "qapi/error.h"
|
||||
#include "qemu/guest-random.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
//#define DEBUG_MULDIV
|
||||
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include "qemu/int128.h"
|
||||
#include "qemu/atomic128.h"
|
||||
#include "tcg/tcg.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
|
||||
{
|
||||
|
|
|
@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
|
|||
'seg_helper.c',
|
||||
'smm_helper.c',
|
||||
'svm_helper.c',
|
||||
'tcg-cpu.c',
|
||||
'translate.c'), if_false: files('tcg-stub.c'))
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include "exec/exec-all.h"
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
|
||||
{
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include "exec/helper-proto.h"
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
|
||||
void helper_bndck(CPUX86State *env, uint32_t fail)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include "exec/exec-all.h"
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "exec/log.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
//#define DEBUG_PCALL
|
||||
|
||||
|
|
|
@ -22,6 +22,8 @@
|
|||
#include "cpu.h"
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/log.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
|
||||
/* SMM support */
|
||||
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include "exec/helper-proto.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/cpu_ldst.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
/* Secure Virtual Machine helpers */
|
||||
|
||||
|
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* i386 TCG cpu class initialization
|
||||
*
|
||||
* Copyright (c) 2003 Fabrice Bellard
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "tcg-cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "sysemu/runstate.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
#include "hw/i386/apic.h"
|
||||
#endif
|
||||
|
||||
/* Frob eflags into and out of the CPU temporary format. */
|
||||
|
||||
static void x86_cpu_exec_enter(CPUState *cs)
|
||||
{
|
||||
X86CPU *cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &cpu->env;
|
||||
|
||||
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
||||
env->df = 1 - (2 * ((env->eflags >> 10) & 1));
|
||||
CC_OP = CC_OP_EFLAGS;
|
||||
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
||||
}
|
||||
|
||||
static void x86_cpu_exec_exit(CPUState *cs)
|
||||
{
|
||||
X86CPU *cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &cpu->env;
|
||||
|
||||
env->eflags = cpu_compute_eflags(env);
|
||||
}
|
||||
|
||||
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
|
||||
{
|
||||
X86CPU *cpu = X86_CPU(cs);
|
||||
|
||||
cpu->env.eip = tb->pc - tb->cs_base;
|
||||
}
|
||||
|
||||
void tcg_cpu_common_class_init(CPUClass *cc)
|
||||
{
|
||||
cc->do_interrupt = x86_cpu_do_interrupt;
|
||||
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
|
||||
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
|
||||
cc->cpu_exec_enter = x86_cpu_exec_enter;
|
||||
cc->cpu_exec_exit = x86_cpu_exec_exit;
|
||||
cc->tcg_initialize = tcg_x86_init;
|
||||
cc->tlb_fill = x86_cpu_tlb_fill;
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
cc->debug_excp_handler = breakpoint_handler;
|
||||
#endif
|
||||
}
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* i386 TCG CPU class initialization
|
||||
*
|
||||
* Copyright 2020 SUSE LLC
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef TCG_CPU_H
|
||||
#define TCG_CPU_H
|
||||
|
||||
void tcg_cpu_common_class_init(CPUClass *cc);
|
||||
|
||||
#endif /* TCG_CPU_H */
|
|
@ -28,6 +28,7 @@
|
|||
|
||||
#include "exec/helper-proto.h"
|
||||
#include "exec/helper-gen.h"
|
||||
#include "helper-tcg.h"
|
||||
|
||||
#include "trace-tcg.h"
|
||||
#include "exec/log.h"
|
||||
|
|
Loading…
Reference in New Issue