There is still a small window that occurs when a cancel I/O affects
an asynchronous I/O operation that hasn't started. In other words,
when the residual data length equals the expected data length.
Today, the routine virtio_scsi_command_complete fails because the
VirtIOSCSIReq pointer (from the hba_private field in SCSIRequest)
was cleared earlier when virtio_scsi_complete_req was called by
the virtio_scsi_request_cancelled routine. As a result, the
virtio_scsi_command_complete routine needs to simply return when
it is processing a SCSIRequest block that was marked canceled.
Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Some emulated disk operations (MODE SELECT, UNMAP, WRITE SAME)
can trigger asynchronous I/Os. Provide the cancel_io callback
to ensure that AIOCBs are properly cleaned up.
Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com>
Cc: qemu-stable@nongnu.org
[Tweak commit message. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This patch uses inbound GPIO lines (IRQ and FIR) for
interrupts instead of using the old pic_cpu method,
which doesn't correspond to real hardware.
This creates the CPU's inbound IRQ and FIR GPIO lines and
updates the Microblaze boards to use this new method.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Suggested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reveiwed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* bonzini/scsi-next:
scsi-disk: add UNMAP limits to block limits VPD page
block/iscsi: use a bh to schedule co reentrance
Message-id: 1387720926-11421-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
* stefanha/block:
commit: Remove unused check
qemu-iotests: Update test cases for commit active
commit: Support commit active layer
block: Add commit_active_start()
mirror: Move base to MirrorBlockJob
mirror: Don't close target
qemu-iotests: drop duplicate virtio-blk initialization failure
vmdk: Allow vmdk_create to work with protocol
vmdk: Check VMFS extent line field number
docs: updated qemu-img man page and qemu-doc to reflect VHDX support.
block: vhdx - improve error message, and .bdrv_check implementation
block/iscsi: Fix compilation for libiscsi 1.4.0 (API change)
qapi-schema: fix QEMU 1.8 references
dataplane: replace hostmem with memory_region_find
dataplane: change vring API to use VirtQueueElement
vring: factor common code for error exits
vring: create a common function to parse descriptors
sheepdog: fix dynamic grow for running qcow2 format
Message-id: 1387554416-5837-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
This includes some Preparatory patches for cpu hotplug for q25 and memory
hotplug by Igor, tests and memory mapping change
by Laszlo and pci reset cleanup by Paolo.
There are also some fixes for fedora and virtio:
included here since they are test blockers for me.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSuF+2AAoJECgfDbjSjVRpTz0IAJhNCC8L2GVt+pm1RAt6lbqZ
u9bCrqfThDORN2mUTEuLu4ZpZC0DYc7d0Jjr5NPesC5G/Afzi5/to6+l7nNZneU3
OdBPglXCCfU/cRaLu7JG2akpha0GVU0tsSCoWIYa6mwlWA4/DXVMgeKg/bh/EgfM
B1w4fE2RgRM9bEqWmX4+tZw8dgk7uVJhu95HCDnb5eikaKlFzwuOlvexrDV3KbPc
bkJe35zbGrKOws93tiSeoqcDx2dcYSzecPoJ0jiCY0KXJ17PBWAvuLTtYqkwwe9J
2FEnTslQJ3Rc8jTFiOPWx2pGaejG4y7Tnk6uuzW6fbbSLOQDPJy3KgmutJFMt1A=
=ShCj
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,fedora,virtio fixes and enhancements
This includes some Preparatory patches for cpu hotplug for q25 and memory
hotplug by Igor, tests and memory mapping change
by Laszlo and pci reset cleanup by Paolo.
There are also some fixes for fedora and virtio:
included here since they are test blockers for me.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Mon 23 Dec 2013 08:07:18 AM PST using RSA key ID D28D5469
# gpg: Can't check signature: public key not found
* mst/tags/for_anthony:
target-arm: fix build with gcc 4.8.2
virtio: add back call to virtio_bus_device_unplugged
piix: fix 32bit pci hole
qdev: switch reset to post-order
qdev: allow both pre- and post-order vists in qdev walking functions
pci: clean up resetting of IRQs
pci: do not export pci_bus_reset
ACPI/DSDT-CPU: cleanup bogus comment
ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handler
acpi: ich9: allow guest to clear SCI rised by GPE
acpi: factor out common pm_update_sci() into acpi core
acpi: piix4: remove not needed GPE0 mask
i440fx-test: verify firmware under 4G and 1M, both -bios and -pflash
i440fx-test: generate temporary firmware blob
i440fx-test: give each GTest case its own qtest
i440fx-test: qtest_start() should be paired with qtest_end()
hw/i386/pc_sysfw: support two flash drives
pc_piix: document gigabyte_align
piix: gigabyte alignment for ram
Message-id: 1387815007-1272-1-git-send-email-mst@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
* QOM interface fixes and unit test
* Device no_user sanitization and documentation
* Device error reporting improvement
* Conversion of APIC, ICC, IOAPIC to QOM realization model
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSub6FAAoJEPou0S0+fgE/JGcP/RvIMVyldoUN1buS+ynXkNGS
UXCwnGGwE6dw7V8eTHxgm7vj1SznaIFZd1jxhbU/PSRn7SkLjHhM4Ei5Nu06nsJD
Dwe22muiGxPIucnwhhuyPni9gP386yR7/4cwqMqvEuB696ZO7tdcMQ4PxwMWW6GN
8XsgF/3nlNFYTTxkG5KhmqqYEQdoQc5aloR7BZiziNaSIXLgIKAFp/T3vl+cwOyV
j2N4Wq+egPNA821Y+sb9V8ZDkwQamE4qsSdIvWSaR24vFEQ8D+U6Sll2qkfcKo4H
dmVu27OYFGJ4hJfyNoJ+7RKF1ET+IcmPW6Hcdri0CZNg5f3rHWur3mvasEMB3I3S
sSQNfItp2bSj0LlTnOcbjE7kP3DTrunAoQ9TJaHo9N94sjXwr8EnCIwHqOZODZbr
j07uKaRyQp4BCSQwP5QP4XEirLvzJOYCxCmT9pXELW/DMjgzjl1XgZVtEowvzHx4
JNoF9mVGjVLDdwb9Tm+nR+9dQsNiGyF7HUYfIf1EwKshp6kwqOmO+YkNKq05kfRN
0GhQB5exB6xN4zUqZTQ544WxB+hls6bOXpOlbKAEWQWpJ2Gj2hlBYTPCuFMwWrfl
rH0jhC9zzlNqRyTUN+KZjU3GTa0T6neOSIXtDiS/VXWKDEV35zohYgwdpAfvpse2
61a4MkgXwy7eqUeZ0Jqu
=WrhM
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging
QOM infrastructure fixes and device conversions
* QOM interface fixes and unit test
* Device no_user sanitization and documentation
* Device error reporting improvement
* Conversion of APIC, ICC, IOAPIC to QOM realization model
# gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg: aka "Andreas Färber <afaerber@suse.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F
* afaerber/tags/qom-devices-for-anthony: (24 commits)
qdev-monitor: Improve error message for -device nonexistant
ioapic: QOM'ify ioapic
ioapic: Cleanup for QOM'ification
icc_bus: QOM'ify ICC
apic: QOM'ify APIC
apic: Cleanup for QOM'ification
qdev: Drop misleading qbus_free() function
qom: Detect bad reentrance during object_class_foreach()
tests: Test QOM interface casting
qom: Do not register interface "types" in the type table and fix names
qom: Split out object and class caches
qdev: Document that pointer properties kill device_add
hw: cannot_instantiate_with_device_add_yet due to pointer props
qdev-monitor: Avoid device_add crashing on non-device driver name
qdev: Do not let the user try to device_add when it cannot work
isa: Clean up use of cannot_instantiate_with_device_add_yet
vt82c686: Clean up use of cannot_instantiate_with_device_add_yet
piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet
ich9: Document why cannot_instantiate_with_device_add_yet
pci-host: Consistently set cannot_instantiate_with_device_add_yet
...
* mjt/trivial-patches:
acpi unit-test: Remove temporary disk after test
mainstone: Fix duplicate array values for key 'space'
pxa27x: Add 'const' attribute to keyboard maps
pxa27x: Reduce size of keyboard matrix mapping
doc: Mention chardev:id in available devices for -serial
configure: Python tests must be done before help message
configure: Rewrite code for help message
fix -boot strict regressed in commit 6ef4716
vl: make boot_strict variable static (not used outside vl.c)
x86: only allow real mode to access 32bit without LMA
linux-user: Use macro TARGET_NSIG_WORDS where possible
exynos4210: Use macro ARRAY_SIZE where possible
ui/cocoa: Use macro ARRAY_SIZE where possible
misc: Use macro ARRAY_SIZE where possible
openrisc: Fix spelling in comment (transaltion -> translation)
hw/arm/highbank: Simplify code (memory region in device state)
Message-id: 1388182050-10270-1-git-send-email-mjt@msgid.tls.msk.ru
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this function to set the priority of
interrupts.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to
make the code comprehensible without looking up the data structure.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not attached to a network.
This allows for probing of the device by expectant guests (such as
OS's). This is needed because sysbus (or AXI in Xilinx's real hw case)
is not self identifying so the guest has no dynamic way of detecting
device absence.
Also allows for testing of the GEM in loopback mode with -net none.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 55649779a68ee3ff54b24c339b6fdbdccd1f0ed7.1388800598.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 4bea048b3ab38425701d82ccc1ab92545c26b79c.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:
Normal mode: RxFIFO vacancy.
Remote loopback: TxFIFO vacancy.
Echo mode: The min of the TxFIFO and RxFIFO vacancies.
Local Loopback: Return non-zero (to implement droppage)
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 36a58440c9ca5080151e95765c2c81342de8a8df.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting
characters instantaneously. There is also no sense of multiple character
delay.
The only side effect of this timer is assertion of tx-empty status. So
just remove the timer completely and hold tx-empty as permanently
asserted (its reset status). This matches the actual behaviour of
instantaneous transmission.
While we are VMSD version bumping, add the tx_fifo as device state to
prepare for upcomming TxFIFO flow control. Implement the interrupt
generation logic for the TxFIFO occupancy.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 7a208a7eb8d79d6429fe28b1396c3104371807b2.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 321994929f789096975104f99c55732774be4cae.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This is a boiler-plate _nofail variant of qemu_opts_create. Remove and
use error_abort in call sites.
null/0 arguments needs to be added for the id and fail_if_exists fields
in affected callsites due to argument inconsistency between the normal and
no_fail variants.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
Replace assert_no_error() usages with the error_abort system.
&error_abort is passed into API calls to signal to the Error sub-system
that any errors are fatal. Removes need for caller assertions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
This is unreachable code, as it's already asserted that no errors have
occurred. Delete.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to 'space'.
QEMU uses the reversed mapping and does not map 'space' to two different
matrix positions.
Some other keys are either missing or might be mapped wrongly (cf. Linux
kernel code). Don't fix these until someone can test them with real
hardware, but add TODO comments.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The mapping is a hardware feature, so it is relatively constant.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Convert 'init' function to QOM's 'realize' for ioapic and kvm-ioapic.
Change variable 'ioapic_no' from static to global. Then we can drop
the 'instance_no' function argument.
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Some cleanups:
* ioapic_common.c: Rename 'register_types' to 'ioapic_common_register_types'
* Replace inline 'DEVICE(s)' with local 'DeviceState *dev' variable
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Convert 'init' function to QOM's 'realize' for apic, kvm/apic and
xen/xen_apic.
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Do some cleanup, including:
1. Remove DO_UPCAST() for APICCommonState
2. Change DeviceState pointers from 'd' to 'dev', better to understand
3. Rename 'register_types' to specifically 'apic_common_register_types'
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Same reasoning as commit 02a5c4c974
("qdev: Drop misleading qdev_free() function"). The qbus_free()
function removes the child from the namespace and decrements the
reference count. It does not, however, guarantee to free the child
since the refcount may still be held.
Just call object_unparent() directly.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Pointer properties can be set only by code, not by device_add. A
device with a pointer property can work with device_add only when the
property may remain null.
This is the case for property "interrupt_vector" of device
"etraxfs,pic". Add a comment there.
Set cannot_instantiate_with_device_add_yet for the other devices with
pointer properties, with a comment explaining why.
Juha Riihimäki and Peter Maydell deserve my thanks for making "pointer
property must not remain null" blatantly obvious in the OMAP devices.
Only device "smbus-eeprom" is actually changed. The others are all
sysbus devices, which get cannot_instantiate_with_device_add_yet set
in their abstract base's class init function. Setting it again in
their class init function is technically redundant, but serves as
insurance for when sysbus devices become available with device_add,
and as documentation.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for ETRAX)
Signed-off-by: Andreas Färber <afaerber@suse.de>
This got lost in a rebase.
Reported-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Make the 32bit pci hole start at end of ram, so all possible address
space is covered.
We used to try and make addresses aligned so they are easier to cover
with MTRRs, but since they are cosmetic on KVM, this is probably not
worth worrying about.
Of course the firmware can use less than that. Leaving space unused is
no problem, mapping pci bars outside the hole causes problems though.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This motion is preparing for refactoring vCPU APIC subsequently.
Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This improves readability and simplifies the code.
Cc: Dmitry Solodkiy <d.solodkiy@samsung.com>
Cc: Evgeny Voevodin <e.voevodin@samsung.com>
Cc: Igor Mitsyanko <i.mitsyanko@gmail.com>
Cc: Maksim Kozlov <m.kozlov@samsung.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This improves readability and simplifies the code.
Cc: Anthony Liguori <aliguori@amazon.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The memory region can be included by value instead of by reference in the
device state.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Post-order is the only sensible direction for the reset signals.
For example, suppose pre-order is used and the parent has some data
structures that cache children state (for example a list of active
requests). When the reset method is invoked on the parent, these caches
could be in any state.
If post-order is used, on the other hand, these will be in a known state
when the reset method is invoked on the parent.
This change means that it is no longer possible to block the visit of
the devices, so the callback is changed to return void. This is not
a problem, because PCI was returning 1 exactly in order to achieve the
same ordering that this patch implements.
PCI can then rely on the qdev core having sent a "reset signal" (whatever
that means) to the device, and only do the PCI-specific initialization
with pci_do_device_reset.
MST: fixed up virtio-ccw
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Resetting should be done in post-order, not pre-order. However,
qdev_walk_children and qbus_walk_children do not allow this. Fix
it by adding two extra arguments to the functions.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
pci_device_reset will deassert the INTX pins, and this will make the
irq_count array all-zeroes. Check that this is the case, and remove
the existing loop which might even unsync irq_count and irq_state.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
qbus_reset_all can be used instead. There is no semantic change
because pcibus_reset returns 1 and takes care of the device
tree traversal.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fix bogus CPU hotplug GPE handler.
Make Q35 CPU hotplug GPE handler match PIIX4 one, since
CPU hotplug event is triggered by GPE0.2 register.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
... and rename it into acpi_update_sci() since it changes
SCI on only on PM registers status.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
with all bits cleared and only QEMU itself can set bits there (i.e.
guest can only clear bits in it). So guest can't triger SCI
by setting _STS & _EN bits and there is not reason to mask out not
supported _STS bits since they shouldn't be set by QEMU in the first
place.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This patch allows the user to usefully specify
-drive file=img_1,if=pflash,format=raw,readonly \
-drive file=img_2,if=pflash,format=raw
on the command line. The flash images will be mapped under 4G in their
reverse unit order -- that is, with their base addresses progressing
downwards, in increasing unit order.
(The unit number increases with command line order if not explicitly
specified.)
This accommodates the following use case: suppose that OVMF is split in
two parts, a writeable host file for non-volatile variable storage, and a
read-only part for bootstrap and decompressible executable code.
The binary code part would be read-only, centrally managed on the host
system, and passed in as unit 0. The variable store would be writeable,
VM-specific, and passed in as unit 1.
00000000ffe00000-00000000ffe1ffff (prio 0, R-): system.flash1
00000000ffe20000-00000000ffffffff (prio 0, R-): system.flash0
(If the guest tries to write to the flash range that is backed by the
read-only drive, pflash_update() is never called; various flash
programming/erase errors are returned to the guest instead. See the
callers of pflash_update(), and the initialization of "pfl->ro", in
"hw/block/pflash_cfi01.c".)
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Map 3G (i440fx) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure this change doesn't take
away memory from 32bit guests.
So, with i440fx and up to 3.5 GB of memory, all of it will be mapped
below 4G. With more than 3.5 GB of memory 3 GB will be mapped below
4G and the remaining amount will be mapped above 4G.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Drop it when there's no obvious reason why device_add could not work.
Else keep and document why.
* isa-fdc: drop
* i8042: drop, even though its I/O base is hardcoded (because you
could conceivably still add one to a board that has none), and even
though PC board code wires up the A20 line (because that wiring is
optional)
* port92: keep because it needs additional wiring by port92_init()
* mc146818rtc: keep because it needs to be wired up by rtc_init()
* m48t59_isa: keep because needs to be wired up by m48t59_init_isa()
* isa-pit, kvm-pit: keep (in their abstract base pic-common) because
the PIT needs additional wiring by board code, depending on HPET
presence
* pcspk: keep because of pointer property pit, and because realize
sets global pcspk_state
* vmmouse: keep because of pointer property ps2_mouse
* vmport: keep because realize sets global port_state
* isa-i8259, kvm-i8259: keep (in their abstract base pic-common),
because the PICs' IRQ input lines are set up by board code, and the
wiring of the slave to the master is hard-coded in device model code
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
A VT82C686B southbridge has multiple functions. We model each
function as a separate qdev. One of them need some special wiring set
up in mips_fulong2e_init() to work: the ISA bridge at 05.0.
The IDE controller at 05.1 (via-ide) has always had
cannot_instantiate_with_device_add_yet set, but there is no obvious
reason why device_add could not work for them. Drop it.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
A PIIX3/PIIX4 southbridge has multiple functions. We model each
function as a separate qdev. Two of them need some special wiring set
up in pc_init1() or mips_malta_init() to work: the ISA bridge at 01.0,
and the SMBus controller at 01.3.
The IDE controller at 01.1 (piix3-ide, piix3-ide-xen, piix4-ide) has
always had cannot_instantiate_with_device_add_yet set, but there is no
obvious reason why device_add could not work for them. Drop it.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
An ICH9 southbridge contains several PCI devices, some of them with
multiple functions. We model each function as a separate qdev. Two
of them need some special wiring set up in pc_q35_init() to work: the
LPC controller at 00:1f.0, and the SMBus controller at 00:1f.3.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
device_add plugs devices into suitable bus. For "real" buses, that
actually connects the device. For sysbus, the connections need to be
made separately, and device_add can't do that. The device would be
left unconnected, and could not possibly work.
Quite a few, but not all sysbus devices already set
cannot_instantiate_with_device_add_yet in their class init function.
Set it in their abstract base's class init function
sysbus_device_class_init(), and remove the now redundant assignments
from device class init functions.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
In an ideal world, machines can be built by wiring devices together
with configuration, not code. Unfortunately, that's not the world we
live in right now. We still have quite a few devices that need to be
wired up by code. If you try to device_add such a device, it'll fail
in sometimes mysterious ways. If you're lucky, you get an
unmysterious immediate crash.
To protect users from such badness, DeviceClass member no_user used to
make device models unavailable with -device / device_add, but that
regressed in commit 18b6dad. The device model is still omitted from
help, but is available anyway.
Attempts to fix the regression have been rejected with the argument
that the purpose of no_user isn't clear, and it's prone to misuse.
This commit clarifies no_user's purpose. Anthony suggested to rename
it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which
I shorten somewhat to keep checkpatch happy. While there, make it
bool.
Every use of cannot_instantiate_with_device_add_yet gets a FIXME
comment asking for rationale. The next few commits will clean them
all up, either by providing a rationale, or by getting rid of the use.
With that done, the regression fix is hopefully acceptable.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Linux prefers WRITE SAME to UNMAP if the limits are zero, and WRITE
SAME does not discard anything unless the device can guarantee that
the resulting block is zero.
Setting the maximum unmap block and descriptor counts to non-zero
makes Linux choose UNMAP and fixes thin provisioning on glusterfs.
While the maximum unmap block count can have some effect on performance,
the (suggested) maximum number of descriptors is not particularly
important so I didn't add a customization option. SCSI drivers are
used to online firmware updates so I'm not yet adding versioning support
for SCSI, but we're probably getting close to the point when it's worth
thinking about it.
Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This makes sure that all NUMA memory blocks reside within RAM or
have zero length.
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory block reported in
the LPAR’s device tree.
So SLOF only maps the first block and that block needs to span
the full RMA.
This makes sure that the RMA area is where SLOF expects it.
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
The qemu_devtree API is a wrapper around the fdt_ set of APIs.
Rename accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[agraf: also convert hw/arm/virt.c]
Signed-off-by: Alexander Graf <agraf@suse.de>
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to ensure that after reboot we
don't happen to execute stale bits from the instruction cache.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
This fixes random reboot issues on e5500 (booke ppc) for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=<drivename>" option. Instead, tie it to -pflash like
other non-volatile RAM devices. This provides the following possibilities
for adding a backend for the sPAPR non-volatile RAM:
* -pflash filename
* -drive if=pflash,file=filename,format=raw,...
* -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").
The big downside to calling it different from anyone else is that tools
that pass -device get confused. They are looking for a bus "pci.0" rather
than "pci".
To make life easier for everyone, let's just drop the name override.
Signed-off-by: Alexander Graf <agraf@suse.de>
This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.
The only parameter handled at the moment is
"platform-processor-diagnostics-run-mode" which is always disabled and
does not support changing. This is expected to make
"ppc64_cpu --run-mode=1" happy.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
[agraf: s/papameter/parameter/g]
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com
[PMM: don't try to load ROM blob if qtest_enabled()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic Lantern (http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1385645602-18662-7-git-send-email-peter.maydell@linaro.org
[PMM:
* updated to use ARMInsnFixup style bootloader fragments
* dropped virt.c additions
* use runtime checks for "is this an AArch64 core" rather than ifdefs
* drop some unnecessary setting of registers in reset hook
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fragment, so switch to a more
flexible scheme where instead of a raw array of instructions we use
an array of (instruction, fixup-type) pairs that indicate which
words need special action or data written into them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1385645602-18662-6-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8db7d57ebe5418fed397fcc86ea719f98446c178.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: e57658b4506b26ab6b6fadbe6d7827f669f51895.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---
Which disappears with this patch.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: fedec366aaa512d75093635f523d1dbcb3358361.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8c671e500390c8be0cc363e887e32867d1d1b0d2.1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max widths
as required. The reading of these IDs uses the same max_width
dependent addressing as CFI queries.
The old code remains for chips that don't specify a device width,
as the new code relies on a device width being set in order to
properly operate. The existing code seems very broken.
Only ident0 and ident1 are used in the new code, as other fields
relate to the lock state of blocks in flash.
The VExpress flash configuration has been updated to match
the new code, as the existing definition was 'wrong' in order
to return the expected results with the broken device ID code.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-8-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Support is also
added for multi-width devices in a x8 configuration. This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should be supported as well if they
exist.
The query response data is now replicated per-device in the bank,
and is adjusted for x16 or x32 parts configured in x8 mode.
The existing code is left in place for boards that have not
been updated to specify an explicit device_width. The VExpress
board has been updated in an earlier patch in this series so
this is the only board currently affected.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-7-git-send-email-roy.franz@linaro.org
[PMM: fixed a few formatting nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is x16 parts that also support x8 mode. When configured for x8
operation these devices respond to CFI and device ID requests differently
than native x8 NOR parts.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-6-git-send-email-roy.franz@linaro.org
[PMM: Added comment explaining the semantics of width vs device-width
vs max-device-width]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform. This change is required for
buffered flash writes to work properly.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-5-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-4-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-3-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1386279359-32286-2-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Hard reset can happen at any time. We should be able to put qxl into a
known-good state no matter what. Stop spice server thread for reset so
it can't be confused by fetching stale commands lingering around in the
rings while we reset is ongoing.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Most notably this includes changes to exec to support
full 64 bit addresses.
This also flushes out patches that got queued during 1.7 freeze.
There are new tests, and a bunch of bug fixes all over the place.
There are also some changes mostly useful for downstreams.
I'm also listing myself as pc co-maintainer. I'm doing this reluctantly,
but this seems to be necessary to make sure patches are not lost or delayed too
much, and posting the MAINTAINERS patch did not seem to make anyone else
volunteer.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSqK0/AAoJECgfDbjSjVRpz0wH/2BCUmgQ8oZfe9PrRhdCpYbw
6RtDLVucIUNq3CYfeV+Lua1Dw62CPVNGUR1Y2sk9s5X0C/lHLXeUkZxYy0JezGmW
k0EZAcVC4kXqyPbVh83I2pKtTwLGfI6I1qzsLZc+6CDT34YN7Lwe+wRJXQQNGcJc
gEbe4U8xuufdPZO2zv9RWEwmI4tI38PxnDJw+MYNJOKNnweLBRKq10YEKrref7Ml
4O1GxAXfQd0wkAhr9Cm7ZBajOzy/ovLj/b7HmiCMOvGkOaVhzurqbOtxlsbVIF9T
26+HEhu+2H/NO4qk5VmZjSngayUySBdEbGLHiovd8Xl4zMFPFNfQXv1mR3Vzb20=
=GPZ/
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi.pci,pc,memory core fixes
Most notably this includes changes to exec to support
full 64 bit addresses.
This also flushes out patches that got queued during 1.7 freeze.
There are new tests, and a bunch of bug fixes all over the place.
There are also some changes mostly useful for downstreams.
I'm also listing myself as pc co-maintainer. I'm doing this reluctantly,
but this seems to be necessary to make sure patches are not lost or delayed too
much, and posting the MAINTAINERS patch did not seem to make anyone else
volunteer.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Wed 11 Dec 2013 10:21:51 AM PST using RSA key ID D28D5469
# gpg: Can't check signature: public key not found
# By Michael S. Tsirkin (14) and others
# Via Michael S. Tsirkin
* mst/tags/for_anthony: (28 commits)
pc: use macro for HPET type
hpet: fix build with CONFIG_HPET off
acpi unit-test: adjust the test data structure for better handling
acpi unit-test: load and check facs table
exec: separate sections and nodes per address space
memory.c: bugfix - ref counting mismatch in memory_region_find
hpet: enable to entitle more irq pins for hpet
hpet: inverse polarity when pin above ISA_NUM_IRQS
pci: fix pci bridge fw path
ACPI DSDT: Make control method `IQCR` serialized
acpi: strip compiler info in built-in DSDT
acpi unit-test: verify signature and checksum
smbios: Set system manufacturer, product & version by default
exec: reduce L2_PAGE_SIZE
exec: make address spaces 64-bit wide
exec: memory radix tree page level compression
exec: pass hw address to phys_page_find
exec: extend skip field to 6 bit, page entry to 32 bit
exec: replace leaf with skip
split definitions for exec.c and translate-all.c radix trees
...
Message-id: cover.1386786228.git.mst@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
# By Paolo Bonzini (4) and Peter Lieven (1)
# Via Paolo Bonzini
* bonzini/scsi-next:
help: add id suboption to -iscsi
scsi-disk: fix WRITE SAME with large non-zero payload
block/iscsi: introduce bdrv_co_{readv, writev, flush_to_disk}
scsi-disk: fix VERIFY emulation
scsi-bus: fix transfer length and direction for VERIFY command
Message-id: 1386594157-17535-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
make hpet_find inline so we don't need
to build hpet.c to check if hpet is enabled.
Fixes link error with CONFIG_HPET off.
Cc: qemu-stable@nongnu.org
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Owning to some different hardware design, piix and q35 need
different compat. So making them diverge.
On q35, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23
can be assigned to hpet as guest chooses. So we introduce intcap
property to do that.
Consider the compat and piix/q35, we finally have the following
value for intcap: For piix, hpet's intcap is hard coded as IRQ2.
For pc-q35-1.7 and earlier, we use IRQ2 for compat reason. Otherwise
IRQ2, IRQ8, and IRQ16~23 are allowed.
Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
According to hpet spec, hpet irq is high active. But according to
ICH spec, there is inversion before the input of ioapic. So the OS
will expect low active on this IRQ line. (On bare metal, if OS driver
claims high active on this line, spurious irq is generated)
We fold the emulation of this inversion inside the hpet logic.
Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
qemu uses "pci" as name for pci bridges in the firmware device path.
seabios expects "pci-bridge". Result is that bootorder is broken for
devices behind pci bridges.
Some googling suggests that "pci-bridge" is the correct one. At least
PPC-based Apple machines are using this. See question "How do I boot
from a device attached to a PCI card" here:
http://www.netbsd.org/ports/macppc/faq.html
So lets change qemu to use "pci-bridge" too.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# By Vincenzo Maffione (2) and others
# Via Stefan Hajnoczi
* stefanha/net-next:
net: Update netdev peer on link change
virtio-net: don't update mac_table in error state
MAINTAINERS: Add netmap maintainers
net: Adding netmap network backend
Message-id: 1386594692-21278-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Emulation bugfixes for intel-hda and adlib.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSpc3gAAoJEEy22O7T6HE4D6IQAKHNCUutcopMEcHJwkldpHqO
uEVdNJvX91ZlgNGOWHtfqzMjRLftZVrY4XHL/D0H/LqXDeShXaT2Kz+6OOKDIDXi
KOchgKf2w3/lbuVtKv3xQSPt2A7TdgJFmfPpbn8f4I6tq6NrTP2TVodOyLc4RF8U
tfo+RDzZIQC5fsBFK284Ngk0abaTpRfWcNpccPh2FXznbCcgt5RiRW1bDPbjLRKD
6QoRyZsyEHAqap49YTSzW7HQFJzSsQX48Oo+FQPU/B81kUYEL7F9sSCam3NpNkoZ
xugn35cavGyYJE2kBmAYj/fMp4fdug8O9P/RZV6GxpDsA7OKimjq7xUxjYS+KtFB
0zdd4ToeheJK7t85kKh2xe30xVIYjffIqwg91LJrFJmlvqbgPKR/K+aY+pVVOKv6
S7lJscFJuBMPAxteb0ajuKZQmaK6P5LC1ckcJSsKPVehqQMzxTYdD9wsv6NN4tRk
ZHDVZEitV+u97fWj/fGjxWPuSMBQwwlbmjyBCn4TOL1iNqdeaW30bLafKBZhdXb9
iUaYMkCWI9dOtMYhkzyIAfPfJCdaMMf12ML+2zEskjll45R8lf+takHXnbeIr8oO
YSe5hWdZzHCdosCOtRJB9UmzbY+EmycsFpsIPsEnSE9Tfg0CXfjnowOGveZ4ikff
UZwqKbNaOAOTpmxM9SV8
=zExI
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'kraxel/tags/pull-audio-1' into staging
Change audio wakeup rate from 250 Hz to 100 Hz.
Emulation bugfixes for intel-hda and adlib.
# gpg: Signature made Mon 09 Dec 2013 06:04:16 AM PST using RSA key ID D3E87138
# gpg: Can't check signature: public key not found
# By Gerd Hoffmann (2) and others
# Via Gerd Hoffmann
* kraxel/tags/pull-audio-1:
intel-hda: fix position buffer
adlib: fix patching of port I/O addresses
audio: adjust pulse to 100Hz wakeup rate
audio: Lower default wakeup rate to 100 times / second
Message-id: 1386597974-26506-1-git-send-email-kraxel@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Return false from can_receive() when no valid buffer descriptor is
available. Ensures against mass packet droppage in some applications.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cde00ef774e84e2586bf10fd37b542f75bf36cfb.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Currently this just floods indicating that can_receive has been called
by the net framework. Instead, save the result of the most recent
can_receive callback as state and only print a message if the result
changes (indicating some sort of actual state change in GEM). Make said
debug message more meaningful as well.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2eb74ca6a5756aea242d9f525961db95d6cfcf2c.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1 or not. i.e. it
was implementing a write-anything-to-clear strategy.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ed905b04d3343966ded425f06aa2224bc7a35b59.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The minimum packet size is 64, however this is before FCS stripping
occurs. So when FCS stripping the minimum packet size is 60. Fix.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 8aac5bd737f9cf48b87f32943d7eb5939061e546.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Bytes_to_copy was being updated before its final use where it
advances the rx buffer pointer. This was causing total mayhem,
where packet data for any subsequent fragments was being fetched
from the wrong place.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: c2a1c65c1fd06eb274442a0fa4a6839d940e145e.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The Specific address registers can be enabled or disabled by software.
QEMU was assuming they were always enabled. Implement the
disable/enable feature. SARs are disabled by writing to the lower half
register. They are re-enabled by then writing the upper half.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 49efd1f7450af8f980b967d3054245bae137866c.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.
This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 7e3f26fc4ab244e8123efc12723e7164730abdcb.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The various Rx packet address matching mode flags were not being set in
the rx descriptor. Implement.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 6002a24a6a8ceaa11d3009ab5392840d1c084b28.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The real hardware prefetches rx buffer descriptors ASAP and
potentially throws relevant interrupts following the fetch
even in the absence of a received packet.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 41629e35edfdb1f02f1e401f2c3d0e2e4c9e44b3.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
There was a replication of the rx descriptor address walking logic.
Reorder the flow control to remove. This refactoring also obsoletes
the local variables packet_desc_addr and last_desc_addr.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2a425b457ff0b57274bf206ad2236690cd7f5909.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
We were updating the ownership bit of all descriptors if packets
get split and written through several descriptors.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: d61b7847b51487118783c93765a485bc5c66d272.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cadence GEM has a MAC level loopback mode. Implement. Use the same basic
operation as the already implemented PHY loopback.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 3a0baf1b6b2fc1be638bdf1a37408ec38988e970.1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Support -cpu host in virt machine (treating it like an A15, ie
with a GIC v2 and the A15's private peripherals.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1385140638-10444-12-git-send-email-peter.maydell@linaro.org
Add 'virt' platform support corresponding to arch/arm/mach-virt
in the Linux kernel tree. This has no platform-specific code but
can use any device whose kernel driver is is able to work purely
from a device tree node. We use this to instantiate a minimal
set of devices: a GIC and some virtio-mmio transports.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1385140638-10444-8-git-send-email-peter.maydell@linaro.org
[PMM:
Significantly overhauled:
* renamed user-facing machine to just "virt"
* removed the A9 support (it can't work since the A9 has no
generic timers)
* added virtio-mmio transports instead of random set of 'soc' devices
(though we retain a pl011 UART)
* instead of updating io_base as we step through adding devices,
define a memory map with an array (similar to vexpress)
* similarly, define irqmap with an array
* folded in some minor fixes from John's aarch64-support patch
* rather than explicitly doing endian-swapping on FDT cells,
use fdt APIs that let us just pass in host-endian values
and let the fdt layer take care of the swapping
* miscellaneous minor code cleanups and style fixes
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
If no fdt is provided on command line and the new field
get_dtb in struct arm_boot_info is set then call it to
get a device tree blob.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1385140638-10444-4-git-send-email-peter.maydell@linaro.org
[PMM: minor tweaks and cleanup]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add the global timer to A9 MPCore.
Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ff92f35f438ac671b57d99d823723dd3e62d2c49.1385969450.git.peter.crosthwaite@xilinx.com
[PC Changes:
* new commit message
* split off original version as a separate patch
* Rebased against new mpcore implementation (with struct embedding)
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The ARM A9 MPCore has a timer that is global to all cores in the cluster.
The timer is shared but each core has a private independent comparator
and interrupt.
Based on version contributed by Francois LEGAL.
Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Message-id: 4918e89476b8da916be2964ec41578b50d569a37.1385969450.git.peter.crosthwaite@xilinx.com
[PC changes:
* New commit message
* Re-implemented as single timer model
* Fixed backwards counting issue in polled mode
* completed VMSD fields
* macroified magic numbers (and headerified reg definitions)
* split of as device-model-only patch
* use bitops for 64 bit register access
* Fixed auto increment mode to check condition properly
* general cleanup (names/style etc).
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[PMM:
* minor typo fixes
* added missing return after error_setg()
* dropped setting dc->no_user = 1
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
To make it consistent for easier code reading. The order in which
variables are defined and functions are called is set to match the
address map ordering.
The new consistent order of doing stuff is:
SCU -> GIC -> MPTimer -> WDT.
0 functional change.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8f31398e6d9a93f57291399f269039da1a77a2b5.1385969450.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename this variable for consistency with the above defined mptimerdev
variable.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 28939ef95589a62414634e86c47cef76b21b15f7.1385969450.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Linux kernel from version 3.4 requires CM_REFCNT register for sched timer
for Integrator/CP board (integrator_defconfig).
See http://infocenter.arm.com/help/topic/com.arm.doc.dui0138e/ch04s06s11.html
Signed-off-by: Jan Petrous <jan.petrous@tieto.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Forward-port the following commit from seabios:
commit 995bbeef78b338370f426bf8d0399038c3fa259c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date: Thu Oct 3 11:30:52 2013 +0200
The ASL Optimizing Compiler version 20130823-32 [Sep 11 2013] issues the
following warning.
$ make
[…]
Compiling IASL out/src/fw/acpi-dsdt.hex
out/src/fw/acpi-dsdt.dsl.i 360: Method(IQCR, 1, NotSerialized) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
[…]
ASL Input: out/src/fw/acpi-dsdt.dsl.i - 475 lines, 19181 bytes, 316 keywords
AML Output: out/src/fw/acpi-dsdt.aml - 4407 bytes, 159 named objects, 157 executable opcodes
Listing File: out/src/fw/acpi-dsdt.lst - 143715 bytes
Hex Dump: out/src/fw/acpi-dsdt.hex - 41661 bytes
Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 246 Optimizations
[…]
After changing the parameter from `NotSerialized` to `Serialized`, the
remark is indeed gone and there is no size change.
The remark was added in ACPICA version 20130517 [1] and gives the
following explanation.
If a thread blocks within the method for any reason, and another thread
enters the method, the method will fail because an attempt will be
made to create the same (named) object twice.
In this case, issue a remark that the method should be marked
serialized. ACPICA BZ 909.
[1] ba84d0fc18
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reported-by: Marcel Apfelbaum <marcel.a@redhat.com>
Tested-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
IASL stores it's revision in each table header it generates.
That's not nice since guests will see a change each time they move
between hypervisors. We generally fill our own info for tables, but we
(and seabios) forgot to do this for the built-in DSDT.
Modifications in DSDT table:
OEM ID: "BXPC" -> "BOCHS "
OEM Table ID: "BXDSDT" -> "BXPCDSDT"
Compiler ID: "INTL" -> "BXPC"
Compiler Version: 0x20130823 -> 0x00000001
Tested-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Currently, we get SeaBIOS defaults: manufacturer Bochs, product Bochs,
no version. Best SeaBIOS can do, but we can provide better defaults:
manufacturer QEMU, product & version taken from QEMUMachine desc and
name.
Take care to do this only for new machine types, of course.
Note: Michael Tsirkin doesn't trust us to keep values of QEMUMachine member
product stable in the future. Use copies instead, and in a way that
makes it obvious that they're guest ABI.
Note that we can be trusted to keep values of member name, because
that has always been ABI.
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
It doesn't make sense for a region to be INT64_MAX in size:
memory core uses UINT64_MAX as a special value meaning
"all 64 bit" this is what was meant here.
While this should never affect the spapr system which at the moment always
has < 63 bit size, this makes us hit all kind of corner case bugs with
sub-pages, so users are probably better off if we just use UINT64_MAX
instead.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Alexander Graf <agraf@suse.de>
It doesn't make sense for a region to be INT64_MAX in size:
memory core uses UINT64_MAX as a special value meaning
"all 64 bit" this is what was meant here.
While this should never affect the PC system which at the moment always
has < 63 bit size, this makes us hit all kind of corner case bugs with
sub-pages, so users are probably better off if we just use UINT64_MAX
instead.
Reported-by: Luiz Capitulino <lcapitulino@redhat.com>
Tested-by: Luiz Capitulino <lcapitulino@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Address space size for bridge should be full 64 bit,
so we should use UINT64_MAX not INT64_MAX as it's size.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
With a help of negative memory region priority PCI address space
is mapped underneath RAM regions effectively catching every access
to addresses not mapped by any other region.
It simplifies PCI address space mapping into system address space.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Temporarily allow either VirtioDeviceClass::init or
VirtioDeviceClass::realize.
Introduce VirtioDeviceClass::unrealize for symmetry.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Rename qdev -> dev since that's what realize's argument is called by
convention. No need to keep more "qdev" around than necessary.
Avoid duplicate VIRTIO_DEVICE() cast.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Eric Farman