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target/riscv: remove cpu->cfg.ext_d 

Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).

Remove the old "d" property and 'ext_d' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:38 -03:00 committed by Alistair Francis
parent c00226e1f0
commit ffffd954ba
2 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
target/riscv/cpu.c
View File

@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
riscv_has_ext(env, RVA) &&
cpu->cfg.ext_f && cpu->cfg.ext_d &&
cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.ext_ifencei = true;
@ -881,7 +880,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
error_setg(errp, "D extension requires F extension");
return;
}
@ -901,7 +900,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zve32f = true;
}
if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
@ -961,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
}
if (cpu->cfg.ext_d) {
if (riscv_has_ext(env, RVD)) {
cpu->cfg.ext_zcd = true;
}
}
@ -976,7 +975,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
error_setg(errp, "Zcd extension requires D extension");
return;
}
@ -1164,7 +1163,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_f) {
ext |= RVF;
}
if (riscv_cpu_cfg(env)->ext_d) {
if (riscv_has_ext(env, RVD)) {
ext |= RVD;
}
if (riscv_has_ext(env, RVC)) {
@ -1499,6 +1498,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVA, .enabled = true},
{.name = "c", .description = "Compressed instructions",
.misa_bit = RVC, .enabled = true},
{.name = "d", .description = "Double-precision float point",
.misa_bit = RVD, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;

1
target/riscv/cpu.h
View File

@ -427,7 +427,6 @@ struct RISCVCPUConfig {
bool ext_g;
bool ext_m;
bool ext_f;
bool ext_d;
bool ext_s;
bool ext_u;
bool ext_h;