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target/riscv: remove cpu->cfg.ext_c 

Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).

Remove the old "c" property and 'ext_c' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:37 -03:00 committed by Alistair Francis
parent 4c759943ec
commit c00226e1f0
2 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target/riscv/cpu.c
View File

@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
cpu->cfg.ext_c = true;
cpu->cfg.ext_u = true;
cpu->cfg.ext_s = true;
cpu->cfg.ext_icsr = true;
@ -957,7 +956,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
if (cpu->cfg.ext_c) {
if (riscv_has_ext(env, RVC)) {
cpu->cfg.ext_zca = true;
if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;
@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_d) {
ext |= RVD;
}
if (riscv_cpu_cfg(env)->ext_c) {
if (riscv_has_ext(env, RVC)) {
ext |= RVC;
}
if (riscv_cpu_cfg(env)->ext_s) {
@ -1498,6 +1497,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
{.name = "a", .description = "Atomic instructions",
.misa_bit = RVA, .enabled = true},
{.name = "c", .description = "Compressed instructions",
.misa_bit = RVC, .enabled = true},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
@ -1649,7 +1649,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_c = misa_ext & RVC;
cpu->cfg.ext_s = misa_ext & RVS;
cpu->cfg.ext_u = misa_ext & RVU;
cpu->cfg.ext_h = misa_ext & RVH;

1
target/riscv/cpu.h
View File

@ -428,7 +428,6 @@ struct RISCVCPUConfig {
bool ext_m;
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;