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target/nios2: Do not create TCGv for control registers 

We don't need to reference them often, and when we do it
is just as easy to load/store from cpu_env directly.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-20-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:16:50 -07:00
parent 48da43b258
commit f1ec078f9a
1 changed files with 26 additions and 7 deletions
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33
target/nios2/translate.c
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@ -103,7 +103,7 @@ typedef struct DisasContext {
int mem_idx; int mem_idx;
} DisasContext; } DisasContext;
static TCGv cpu_R[NUM_CORE_REGS]; static TCGv cpu_R[NUM_GP_REGS];
static TCGv cpu_pc; static TCGv cpu_pc;
typedef struct Nios2Instruction { typedef struct Nios2Instruction {
@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
g_assert_not_reached(); g_assert_not_reached();
#else #else
gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS]));
gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
tcg_temp_free(tmp);
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
#endif #endif
} }
@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
g_assert_not_reached(); g_assert_not_reached();
#else #else
gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
tcg_temp_free(tmp);
dc->base.is_jmp = DISAS_NORETURN; dc->base.is_jmp = DISAS_NORETURN;
#endif #endif
} }
@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
{ {
R_TYPE(instr, code); R_TYPE(instr, code);
TCGv t1, t2;
if (!gen_check_supervisor(dc)) { if (!gen_check_supervisor(dc)) {
return; return;
@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
* must perform the AND here, and anywhere else we need the * must perform the AND here, and anywhere else we need the
* guest value of ipending. * guest value of ipending.
*/ */
tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); t1 = tcg_temp_new();
t2 = tcg_temp_new();
tcg_gen_ld_tl(t1, cpu_env,
offsetof(CPUNios2State, regs[CR_IPENDING]));
tcg_gen_ld_tl(t2, cpu_env,
offsetof(CPUNios2State, regs[CR_IENABLE]));
tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
break; break;
default: default:
tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break; break;
} }
} }
@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
dc->base.is_jmp = DISAS_UPDATE; dc->base.is_jmp = DISAS_UPDATE;
/* fall through */ /* fall through */
default: default:
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); tcg_gen_st_tl(v, cpu_env,
offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break; break;
} }
#endif #endif
@ -910,7 +929,7 @@ void nios2_tcg_init(void)
{ {
int i; int i;
for (i = 0; i < NUM_CORE_REGS; i++) { for (i = 0; i < NUM_GP_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env, cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, regs[i]), offsetof(CPUNios2State, regs[i]),
regnames[i]); regnames[i]);