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pnv/xive2: Allow writes to the Physical Thread Enable registers 

Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.

Fixes: da71b7e3ed ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Frederic Barrat 2023-06-01 14:13:29 +02:00 committed by Daniel Henrique Barboza
parent 32af01f83a
commit f0fc1c29a8
1 changed files with 1 additions and 0 deletions
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hw/intc/pnv_xive2.c
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@ -1294,6 +1294,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,
*/
case TCTXT_EN0: /* Physical Thread Enable */
case TCTXT_EN1: /* Physical Thread Enable (fused core) */
xive->tctxt_regs[reg] = val;
break;
case TCTXT_EN0_SET: