mirror of https://github.com/xemu-project/xemu.git
pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register on P10. We don't model the ESB cache in qemu so reading/writing the register won't do anything, but it avoids logging a guest error when skiboot configures it: qemu-system-ppc64 -machine powernv10 ... -d guest_errors ... XIVE[0] - VC: invalid read @240 XIVE[0] - VC: invalid write @240 Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -955,6 +955,10 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset,
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val = xive->vc_regs[reg];
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break;
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case VC_ESBC_CFG:
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val = xive->vc_regs[reg];
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break;
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/*
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* EAS cache updates (not modeled)
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*/
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@ -1046,6 +1050,9 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset,
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/* ESB update */
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break;
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case VC_ESBC_CFG:
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break;
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/*
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* EAS cache updates (not modeled)
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*/
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@ -232,6 +232,10 @@
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#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
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#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
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/* ESBC configuration */
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#define X_VC_ESBC_CFG 0x148
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#define VC_ESBC_CFG 0x240
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/* EASC flush control register */
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#define X_VC_EASC_FLUSH_CTRL 0x160
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#define VC_EASC_FLUSH_CTRL 0x300
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