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tcg/mips tlb lookup fix 

target/alpha icount fix
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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210405' into staging

tcg/mips tlb lookup fix
target/alpha icount fix

# gpg: Signature made Mon 05 Apr 2021 15:34:06 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210405:
  target/alpha: fix icount handling for timer instructions
  tcg/mips: Fix SoftTLB comparison on mips backend

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-04-05 19:29:45 +01:00
parent 25d75c99b2 ef951ee33f
commit ee82c086ba
2 changed files with 8 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target/alpha/translate.c
View File

@ -1330,7 +1330,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
case 249: /* VMTIME */
helper = gen_helper_get_vmtime;
do_helper:
if (icount_enabled()) {
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
helper(va);
return DISAS_PC_STALE;
@ -1366,6 +1366,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)
static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
{
int data;
DisasJumpType ret = DISAS_NEXT;
switch (regno) {
case 255:
@ -1395,6 +1396,10 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
case 251:
/* ALARM */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
ret = DISAS_PC_STALE;
}
gen_helper_set_alarm(cpu_env, vb);
break;
@ -1434,7 +1439,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
break;
}
return DISAS_NEXT;
return ret;
}
#endif /* !USER_ONLY*/

2
tcg/mips/tcg-target.c.inc
View File

@ -1201,13 +1201,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
load the tlb addend for the fast path. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
}
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
/* Zero extend a 32-bit guest address for a 64-bit host. */
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, base, addrl);
addrl = base;
}
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
label_ptr[0] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);