mirror of https://github.com/xemu-project/xemu.git
target/riscv: Add Zvkned ISA extension support
This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Nazar Kazakov
Alistair Francis
parent
0602847289
commit
e972bf22f6
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@ -129,6 +129,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
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ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
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ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
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ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
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ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
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ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
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ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
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@ -1277,7 +1278,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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* In principle Zve*x would also suffice here, were they supported
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* in qemu
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*/
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if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) {
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if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) {
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error_setg(errp,
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"Vector crypto extensions require V or Zve* extensions");
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return;
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@ -1873,6 +1874,7 @@ static Property riscv_cpu_extensions[] = {
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/* Vector cryptography extensions */
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DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false),
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DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false),
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DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -87,6 +87,7 @@ struct RISCVCPUConfig {
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bool ext_zve64d;
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bool ext_zvbb;
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bool ext_zvbc;
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bool ext_zvkned;
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bool ext_zmmul;
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bool ext_zvfbfmin;
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bool ext_zvfbfwma;
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@ -1250,3 +1250,17 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_2(egs_check, void, i32, env)
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DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
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DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
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DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32)
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DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32)
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@ -75,6 +75,7 @@
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@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
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@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
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@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
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@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
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@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
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@ -972,3 +973,16 @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
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vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
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vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
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vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
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# *** Zvkned vector crypto extension ***
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vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
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vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
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vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
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vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
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vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
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vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
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vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
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vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
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vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
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vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
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vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
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@ -224,3 +224,150 @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
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GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
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GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
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GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
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/*
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* Zvkned
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*/
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#define ZVKNED_EGS 4
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#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ \
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if (CHECK(s, a)) { \
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TCGv_ptr rd_v, rs2_v; \
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TCGv_i32 desc, egs; \
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uint32_t data = 0; \
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TCGLabel *over = gen_new_label(); \
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\
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if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
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/* save opcode for unwinding in case we throw an exception */ \
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decode_save_opc(s); \
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egs = tcg_constant_i32(EGS); \
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gen_helper_egs_check(egs, cpu_env); \
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
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} \
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\
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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rd_v = tcg_temp_new_ptr(); \
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rs2_v = tcg_temp_new_ptr(); \
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desc = tcg_constant_i32( \
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simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
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tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
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tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
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gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul) &&
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s->sew == MO_32;
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}
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static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
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{
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int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
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return !is_overlapped(vd, op_size, vs2, 1);
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}
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static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return vaes_check_overlap(s, a->rd, a->rs2) &&
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MAXSZ(s) >= egw_bytes &&
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s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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require_align(a->rd, s->lmul) &&
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s->sew == MO_32;
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}
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GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
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#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ \
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if (CHECK(s, a)) { \
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TCGv_ptr rd_v, rs2_v; \
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TCGv_i32 uimm_v, desc, egs; \
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uint32_t data = 0; \
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TCGLabel *over = gen_new_label(); \
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\
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if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
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/* save opcode for unwinding in case we throw an exception */ \
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decode_save_opc(s); \
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egs = tcg_constant_i32(EGS); \
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gen_helper_egs_check(egs, cpu_env); \
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
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} \
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\
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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\
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rd_v = tcg_temp_new_ptr(); \
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rs2_v = tcg_temp_new_ptr(); \
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uimm_v = tcg_constant_i32(a->rs1); \
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desc = tcg_constant_i32( \
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simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
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tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
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tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
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gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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s->sew == MO_32 &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul);
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}
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static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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s->sew == MO_32 &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul);
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}
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GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
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GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
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@ -22,6 +22,8 @@
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#include "qemu/bitops.h"
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#include "qemu/bswap.h"
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#include "cpu.h"
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#include "crypto/aes.h"
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#include "crypto/aes-round.h"
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#include "exec/memop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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@ -195,3 +197,203 @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL)
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GEN_VEXT_VX(vwsll_vx_b, 2)
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GEN_VEXT_VX(vwsll_vx_h, 4)
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GEN_VEXT_VX(vwsll_vx_w, 8)
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void HELPER(egs_check)(uint32_t egs, CPURISCVState *env)
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{
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uint32_t vl = env->vl;
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uint32_t vstart = env->vstart;
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if (vl % egs != 0 || vstart % egs != 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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}
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static inline void xor_round_key(AESState *round_state, AESState *round_key)
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{
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round_state->v = round_state->v ^ round_key->v;
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}
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#define GEN_ZVKNED_HELPER_VV(NAME, ...) \
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void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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uint32_t vl = env->vl; \
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uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
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uint32_t vta = vext_vta(desc); \
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\
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
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AESState round_key; \
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round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
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round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
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AESState round_state; \
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round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
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round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
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__VA_ARGS__; \
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*((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
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*((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
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} \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
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}
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#define GEN_ZVKNED_HELPER_VS(NAME, ...) \
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void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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uint32_t vl = env->vl; \
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uint32_t total_elems = vext_get_total_elems(env, desc, 4); \
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uint32_t vta = vext_vta(desc); \
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\
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \
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AESState round_key; \
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round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
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round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
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AESState round_state; \
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round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \
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round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \
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__VA_ARGS__; \
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*((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \
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*((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \
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} \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \
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}
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GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state,
|
||||
&round_state,
|
||||
&round_key,
|
||||
false);)
|
||||
GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);)
|
||||
|
||||
void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
|
||||
CPURISCVState *env, uint32_t desc)
|
||||
{
|
||||
uint32_t *vd = vd_vptr;
|
||||
uint32_t *vs2 = vs2_vptr;
|
||||
uint32_t vl = env->vl;
|
||||
uint32_t total_elems = vext_get_total_elems(env, desc, 4);
|
||||
uint32_t vta = vext_vta(desc);
|
||||
|
||||
uimm &= 0b1111;
|
||||
if (uimm > 10 || uimm == 0) {
|
||||
uimm ^= 0b1000;
|
||||
}
|
||||
|
||||
for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
|
||||
uint32_t rk[8], tmp;
|
||||
static const uint32_t rcon[] = {
|
||||
0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
|
||||
0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
|
||||
};
|
||||
|
||||
rk[0] = vs2[i * 4 + H4(0)];
|
||||
rk[1] = vs2[i * 4 + H4(1)];
|
||||
rk[2] = vs2[i * 4 + H4(2)];
|
||||
rk[3] = vs2[i * 4 + H4(3)];
|
||||
tmp = ror32(rk[3], 8);
|
||||
|
||||
rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
|
||||
((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
|
||||
((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
|
||||
((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
|
||||
^ rcon[uimm - 1];
|
||||
rk[5] = rk[1] ^ rk[4];
|
||||
rk[6] = rk[2] ^ rk[5];
|
||||
rk[7] = rk[3] ^ rk[6];
|
||||
|
||||
vd[i * 4 + H4(0)] = rk[4];
|
||||
vd[i * 4 + H4(1)] = rk[5];
|
||||
vd[i * 4 + H4(2)] = rk[6];
|
||||
vd[i * 4 + H4(3)] = rk[7];
|
||||
}
|
||||
env->vstart = 0;
|
||||
/* set tail elements to 1s */
|
||||
vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
|
||||
}
|
||||
|
||||
void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
|
||||
CPURISCVState *env, uint32_t desc)
|
||||
{
|
||||
uint32_t *vd = vd_vptr;
|
||||
uint32_t *vs2 = vs2_vptr;
|
||||
uint32_t vl = env->vl;
|
||||
uint32_t total_elems = vext_get_total_elems(env, desc, 4);
|
||||
uint32_t vta = vext_vta(desc);
|
||||
|
||||
uimm &= 0b1111;
|
||||
if (uimm > 14 || uimm < 2) {
|
||||
uimm ^= 0b1000;
|
||||
}
|
||||
|
||||
for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
|
||||
uint32_t rk[12], tmp;
|
||||
static const uint32_t rcon[] = {
|
||||
0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010,
|
||||
0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036,
|
||||
};
|
||||
|
||||
rk[0] = vd[i * 4 + H4(0)];
|
||||
rk[1] = vd[i * 4 + H4(1)];
|
||||
rk[2] = vd[i * 4 + H4(2)];
|
||||
rk[3] = vd[i * 4 + H4(3)];
|
||||
rk[4] = vs2[i * 4 + H4(0)];
|
||||
rk[5] = vs2[i * 4 + H4(1)];
|
||||
rk[6] = vs2[i * 4 + H4(2)];
|
||||
rk[7] = vs2[i * 4 + H4(3)];
|
||||
|
||||
if (uimm % 2 == 0) {
|
||||
tmp = ror32(rk[7], 8);
|
||||
rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) |
|
||||
((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) |
|
||||
((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) |
|
||||
((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0))
|
||||
^ rcon[(uimm - 1) / 2];
|
||||
} else {
|
||||
rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) |
|
||||
((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) |
|
||||
((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) |
|
||||
((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0));
|
||||
}
|
||||
rk[9] = rk[1] ^ rk[8];
|
||||
rk[10] = rk[2] ^ rk[9];
|
||||
rk[11] = rk[3] ^ rk[10];
|
||||
|
||||
vd[i * 4 + H4(0)] = rk[8];
|
||||
vd[i * 4 + H4(1)] = rk[9];
|
||||
vd[i * 4 + H4(2)] = rk[10];
|
||||
vd[i * 4 + H4(3)] = rk[11];
|
||||
}
|
||||
env->vstart = 0;
|
||||
/* set tail elements to 1s */
|
||||
vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue