mirror of https://github.com/xemu-project/xemu.git
374 lines
19 KiB
C++
374 lines
19 KiB
C++
/*
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* RISC-V translation routines for the vector crypto extension.
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*
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* Copyright (C) 2023 SiFive, Inc.
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* Written by Codethink Ltd and SiFive.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Zvbc
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*/
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#define GEN_VV_MASKED_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
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gen_helper_##NAME, s); \
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} \
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return false; \
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}
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static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
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{
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return opivv_check(s, a) &&
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s->cfg_ptr->ext_zvbc == true &&
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s->sew == MO_64;
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}
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GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check)
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GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check)
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#define GEN_VX_MASKED_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
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gen_helper_##NAME, s); \
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} \
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return false; \
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}
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static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
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{
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return opivx_check(s, a) &&
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s->cfg_ptr->ext_zvbc == true &&
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s->sew == MO_64;
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}
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GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
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GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
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/*
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* Zvbb
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*/
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#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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static gen_helper_opivx *const fns[4] = { \
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gen_helper_##OPIVX##_b, \
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gen_helper_##OPIVX##_h, \
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gen_helper_##OPIVX##_w, \
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gen_helper_##OPIVX##_d, \
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}; \
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return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \
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IMM_MODE); \
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} \
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return false; \
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}
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#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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static gen_helper_gvec_4_ptr *const fns[4] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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gen_helper_##NAME##_d, \
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}; \
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return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
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} \
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return false; \
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}
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#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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static gen_helper_opivx *const fns[4] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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gen_helper_##NAME##_d, \
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}; \
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return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \
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fns[s->sew]); \
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} \
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return false; \
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}
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static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
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{
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return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
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}
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static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
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{
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return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
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}
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/* vrol.v[vx] */
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GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
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GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
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/* vror.v[vxi] */
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GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
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GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
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GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
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#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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static gen_helper_opivx *const fns[4] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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gen_helper_##NAME##_d, \
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}; \
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return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
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} \
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return false; \
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}
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/* vandn.v[vx] */
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GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
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GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
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#define GEN_OPIV_TRANS(NAME, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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{ \
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if (CHECK(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_gvec_3_ptr *const fns[4] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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gen_helper_##NAME##_d, \
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}; \
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TCGLabel *over = gen_new_label(); \
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
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\
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), cpu_env, \
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s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
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data, fns[s->sew]); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
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{
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return s->cfg_ptr->ext_zvbb == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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vext_check_ss(s, a->rd, a->rs2, a->vm);
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}
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GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
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GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
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GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
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GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
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GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
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GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check)
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static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a)
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{
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return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a);
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}
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static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
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{
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return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a);
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}
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/* OPIVI without GVEC IR */
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#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (CHECK(s, a)) { \
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static gen_helper_opivx *const fns[3] = { \
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gen_helper_##OPIVX##_b, \
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gen_helper_##OPIVX##_h, \
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gen_helper_##OPIVX##_w, \
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}; \
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return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
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IMM_MODE); \
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} \
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return false; \
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}
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GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check)
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GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check)
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GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
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/*
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* Zvkned
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*/
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#define ZVKNED_EGS 4
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#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ \
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if (CHECK(s, a)) { \
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TCGv_ptr rd_v, rs2_v; \
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TCGv_i32 desc, egs; \
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uint32_t data = 0; \
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TCGLabel *over = gen_new_label(); \
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\
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if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
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/* save opcode for unwinding in case we throw an exception */ \
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decode_save_opc(s); \
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egs = tcg_constant_i32(EGS); \
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gen_helper_egs_check(egs, cpu_env); \
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
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} \
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\
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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rd_v = tcg_temp_new_ptr(); \
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rs2_v = tcg_temp_new_ptr(); \
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desc = tcg_constant_i32( \
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simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
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tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
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tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
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gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul) &&
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s->sew == MO_32;
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}
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static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
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{
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int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
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return !is_overlapped(vd, op_size, vs2, 1);
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}
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static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return vaes_check_overlap(s, a->rd, a->rs2) &&
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MAXSZ(s) >= egw_bytes &&
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s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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require_align(a->rd, s->lmul) &&
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s->sew == MO_32;
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}
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GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS)
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GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
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#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
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{ \
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if (CHECK(s, a)) { \
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TCGv_ptr rd_v, rs2_v; \
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TCGv_i32 uimm_v, desc, egs; \
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uint32_t data = 0; \
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TCGLabel *over = gen_new_label(); \
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\
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if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
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/* save opcode for unwinding in case we throw an exception */ \
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decode_save_opc(s); \
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egs = tcg_constant_i32(EGS); \
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gen_helper_egs_check(egs, cpu_env); \
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
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} \
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\
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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\
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rd_v = tcg_temp_new_ptr(); \
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rs2_v = tcg_temp_new_ptr(); \
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uimm_v = tcg_constant_i32(a->rs1); \
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desc = tcg_constant_i32( \
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simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
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tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \
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tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \
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gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \
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mark_vs_dirty(s); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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s->sew == MO_32 &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul);
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}
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static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
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{
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int egw_bytes = ZVKNED_EGS << s->sew;
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return s->cfg_ptr->ext_zvkned == true &&
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require_rvv(s) &&
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vext_check_isa_ill(s) &&
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MAXSZ(s) >= egw_bytes &&
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s->sew == MO_32 &&
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require_align(a->rd, s->lmul) &&
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require_align(a->rs2, s->lmul);
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}
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GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS)
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GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
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