mirror of https://github.com/xemu-project/xemu.git
target/mips: Clean up handling of CP0 register 18
Clean up handling of CP0 register 18. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
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* Register 16 Register 17 Register 18 Register 19
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* ----------- ----------- ----------- -----------
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*
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* 0 Config LLAddr WatchLo WatchHi
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* 1 Config1 MAAR WatchLo WatchHi
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* 2 Config2 MAARI WatchLo WatchHi
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* 3 Config3 WatchLo WatchHi
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* 4 Config4 WatchLo WatchHi
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* 5 Config5 WatchLo WatchHi
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* 6 WatchLo WatchHi
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* 7 WatchLo WatchHi
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* 0 Config LLAddr WatchLo0 WatchHi
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* 1 Config1 MAAR WatchLo1 WatchHi
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* 2 Config2 MAARI WatchLo2 WatchHi
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* 3 Config3 WatchLo3 WatchHi
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* 4 Config4 WatchLo4 WatchHi
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* 5 Config5 WatchLo5 WatchHi
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* 6 WatchLo6 WatchHi
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* 7 WatchLo7 WatchHi
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*
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*
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* Register 20 Register 21 Register 22 Register 23
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@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG18__WATCHLO1 1
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#define CP0_REG18__WATCHLO2 2
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#define CP0_REG18__WATCHLO3 3
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#define CP0_REG18__WATCHLO4 4
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#define CP0_REG18__WATCHLO5 5
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#define CP0_REG18__WATCHLO6 6
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#define CP0_REG18__WATCHLO7 7
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/* CP0 Register 19 */
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#define CP0_REG19__WATCHHI0 0
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#define CP0_REG19__WATCHHI1 1
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@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_18:
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switch (sel) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case CP0_REG18__WATCHLO0:
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case CP0_REG18__WATCHLO1:
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case CP0_REG18__WATCHLO2:
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case CP0_REG18__WATCHLO3:
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case CP0_REG18__WATCHLO4:
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case CP0_REG18__WATCHLO5:
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case CP0_REG18__WATCHLO6:
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case CP0_REG18__WATCHLO7:
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CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
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gen_helper_1e0i(mfc0_watchlo, arg, sel);
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register_name = "WatchLo";
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@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_18:
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switch (sel) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case CP0_REG18__WATCHLO0:
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case CP0_REG18__WATCHLO1:
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case CP0_REG18__WATCHLO2:
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case CP0_REG18__WATCHLO3:
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case CP0_REG18__WATCHLO4:
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case CP0_REG18__WATCHLO5:
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case CP0_REG18__WATCHLO6:
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case CP0_REG18__WATCHLO7:
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CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
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gen_helper_0e1i(mtc0_watchlo, arg, sel);
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register_name = "WatchLo";
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@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_18:
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switch (sel) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case CP0_REG18__WATCHLO0:
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case CP0_REG18__WATCHLO1:
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case CP0_REG18__WATCHLO2:
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case CP0_REG18__WATCHLO3:
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case CP0_REG18__WATCHLO4:
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case CP0_REG18__WATCHLO5:
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case CP0_REG18__WATCHLO6:
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case CP0_REG18__WATCHLO7:
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CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
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gen_helper_1e0i(dmfc0_watchlo, arg, sel);
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register_name = "WatchLo";
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@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_18:
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switch (sel) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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case CP0_REG18__WATCHLO0:
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case CP0_REG18__WATCHLO1:
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case CP0_REG18__WATCHLO2:
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case CP0_REG18__WATCHLO3:
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case CP0_REG18__WATCHLO4:
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case CP0_REG18__WATCHLO5:
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case CP0_REG18__WATCHLO6:
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case CP0_REG18__WATCHLO7:
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CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
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gen_helper_0e1i(mtc0_watchlo, arg, sel);
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register_name = "WatchLo";
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