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target/mips: Clean up handling of CP0 register 18 

Clean up handling of CP0 register 18.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:43 +02:00
parent 706ce14205
commit e8dcfe825a
2 changed files with 44 additions and 40 deletions
target/mips
cpu.htranslate.c

20
target/mips/cpu.h
View File

@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
* 0 Config LLAddr WatchLo WatchHi
* 1 Config1 MAAR WatchLo WatchHi
* 2 Config2 MAARI WatchLo WatchHi
* 3 Config3 WatchLo WatchHi
* 4 Config4 WatchLo WatchHi
* 5 Config5 WatchLo WatchHi
* 6 WatchLo WatchHi
* 7 WatchLo WatchHi
* 0 Config LLAddr WatchLo0 WatchHi
* 1 Config1 MAAR WatchLo1 WatchHi
* 2 Config2 MAARI WatchLo2 WatchHi
* 3 Config3 WatchLo3 WatchHi
* 4 Config4 WatchLo4 WatchHi
* 5 Config5 WatchLo5 WatchHi
* 6 WatchLo6 WatchHi
* 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO1 1
#define CP0_REG18__WATCHLO2 2
#define CP0_REG18__WATCHLO3 3
#define CP0_REG18__WATCHLO4 4
#define CP0_REG18__WATCHLO5 5
#define CP0_REG18__WATCHLO6 6
#define CP0_REG18__WATCHLO7 7
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI0 0
#define CP0_REG19__WATCHHI1 1

64
target/mips/translate.c
View File

@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG18__WATCHLO0:
case CP0_REG18__WATCHLO1:
case CP0_REG18__WATCHLO2:
case CP0_REG18__WATCHLO3:
case CP0_REG18__WATCHLO4:
case CP0_REG18__WATCHLO5:
case CP0_REG18__WATCHLO6:
case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG18__WATCHLO0:
case CP0_REG18__WATCHLO1:
case CP0_REG18__WATCHLO2:
case CP0_REG18__WATCHLO3:
case CP0_REG18__WATCHLO4:
case CP0_REG18__WATCHLO5:
case CP0_REG18__WATCHLO6:
case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG18__WATCHLO0:
case CP0_REG18__WATCHLO1:
case CP0_REG18__WATCHLO2:
case CP0_REG18__WATCHLO3:
case CP0_REG18__WATCHLO4:
case CP0_REG18__WATCHLO5:
case CP0_REG18__WATCHLO6:
case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case CP0_REG18__WATCHLO0:
case CP0_REG18__WATCHLO1:
case CP0_REG18__WATCHLO2:
case CP0_REG18__WATCHLO3:
case CP0_REG18__WATCHLO4:
case CP0_REG18__WATCHLO5:
case CP0_REG18__WATCHLO6:
case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";