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target/loongarch: Implement Chip Configuraiton Version Register(0x0000) 

According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x0000).

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-02-27 15:10:46 +08:00
parent 5f4c96b779
commit c77432d0ef
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GPG Key ID: 40A2FFF239263EDF
2 changed files with 3 additions and 0 deletions
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2
target/loongarch/cpu.c
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@ -546,6 +546,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr,
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
{ {
switch (addr) { switch (addr) {
case VERSION_REG:
return 0x11ULL;
case FEATURE_REG: case FEATURE_REG:
return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
1ULL << IOCSRF_CSRIPI; 1ULL << IOCSRF_CSRIPI;

1
target/loongarch/cpu.h
View File

@ -28,6 +28,7 @@
#define IOCSRF_GMOD 9 #define IOCSRF_GMOD 9
#define IOCSRF_VM 11 #define IOCSRF_VM 11
#define VERSION_REG 0x0
#define FEATURE_REG 0x8 #define FEATURE_REG 0x8
#define VENDOR_REG 0x10 #define VENDOR_REG 0x10
#define CPUNAME_REG 0x20 #define CPUNAME_REG 0x20