From c77432d0efc56273347eb5d8619935052e5ad0a6 Mon Sep 17 00:00:00 2001 From: Song Gao Date: Mon, 27 Feb 2023 15:10:46 +0800 Subject: [PATCH] target/loongarch: Implement Chip Configuraiton Version Register(0x0000) According to the 3A5000 manual 4.1 implement Chip Configuration Version Register(0x0000). Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn> --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d6513f2d9d..97e6579f6a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -546,6 +546,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr, static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) { switch (addr) { + case VERSION_REG: + return 0x11ULL; case FEATURE_REG: return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 1ULL << IOCSRF_CSRIPI; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index d60693fafe..e11c875188 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -28,6 +28,7 @@ #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define VERSION_REG 0x0 #define FEATURE_REG 0x8 #define VENDOR_REG 0x10 #define CPUNAME_REG 0x20