mirror of https://github.com/xemu-project/xemu.git
xbox-pci: Add SMBus/LPC/PCI VMStateDescription
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@ -44,6 +44,7 @@
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#include "hw/xbox/amd_smbus.h"
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#include "hw/xbox/xbox_pci.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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/*
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* xbox chipset based on nForce 420, which was based on AMD-760
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@ -258,19 +259,31 @@ static void xbox_smbus_realize(PCIDevice *dev, Error **errp)
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&s->smb_bar);
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}
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static const VMStateDescription vmstate_xbox_smbus = {
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.name = "xbox-smbus",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, XBOX_SMBState),
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// FIXME
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VMSTATE_END_OF_LIST()
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},
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};
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static void xbox_smbus_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = xbox_smbus_realize;
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k->vendor_id = PCI_VENDOR_ID_NVIDIA;
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k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS;
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k->revision = 161;
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k->class_id = PCI_CLASS_SERIAL_SMBUS;
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k->realize = xbox_smbus_realize;
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k->vendor_id = PCI_VENDOR_ID_NVIDIA;
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k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS;
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k->revision = 161;
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k->class_id = PCI_CLASS_SERIAL_SMBUS;
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dc->desc = "nForce PCI System Management";
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dc->desc = "nForce PCI System Management";
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dc->user_creatable = false;
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dc->vmsd = &vmstate_xbox_smbus;
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}
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static const TypeInfo xbox_smbus_info = {
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@ -358,6 +371,17 @@ static void xbox_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
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acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
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}
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static const VMStateDescription vmstate_xbox_lpc = {
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.name = "xbox-lpc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, XBOX_LPCState),
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VMSTATE_STRUCT(pm, XBOX_LPCState, 0, vmstate_xbox_pm, XBOX_PMRegs),
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VMSTATE_END_OF_LIST()
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},
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};
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static void xbox_lpc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -375,7 +399,7 @@ static void xbox_lpc_class_init(ObjectClass *klass, void *data)
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dc->desc = "nForce LPC Bridge";
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dc->user_creatable = false;
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dc->reset = xbox_lpc_reset;
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//dc->vmsd = &vmstate_xbox_lpc;
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dc->vmsd = &vmstate_xbox_lpc;
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adevc->send_event = xbox_send_gpe;
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}
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@ -403,16 +427,17 @@ static void xbox_agp_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = xbox_agp_realize;
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k->exit = pci_bridge_exitfn;
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k->realize = xbox_agp_realize;
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k->exit = pci_bridge_exitfn;
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k->config_write = pci_bridge_write_config;
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k->is_bridge = 1;
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k->vendor_id = PCI_VENDOR_ID_NVIDIA;
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k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_AGP;
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k->revision = 161;
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k->is_bridge = 1;
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k->vendor_id = PCI_VENDOR_ID_NVIDIA;
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k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_AGP;
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k->revision = 161;
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dc->desc = "nForce AGP to PCI Bridge";
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dc->reset = pci_bridge_reset;
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dc->desc = "nForce AGP to PCI Bridge";
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dc->vmsd = &vmstate_pci_device;
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dc->reset = pci_bridge_reset;
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}
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static const TypeInfo xbox_agp_info = {
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@ -431,6 +456,14 @@ static void xbox_pci_realize(PCIDevice *d, Error **errp)
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//XBOX_PCIState *s = DO_UPCAST(XBOX_PCIState, dev, dev);
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}
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static const VMStateDescription pci_bridge_dev_vmstate = {
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.name = "xbox-pci",
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xbox_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -446,6 +479,7 @@ static void xbox_pci_class_init(ObjectClass *klass, void *data)
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dc->desc = "Xbox PCI Host";
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dc->user_creatable = false;
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dc->vmsd = &pci_bridge_dev_vmstate;
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}
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static const TypeInfo xbox_pci_info = {
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@ -2,6 +2,7 @@
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* QEMU Xbox PCI buses implementation
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*
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* Copyright (c) 2012 espes
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* Copyright (c) 2020 Matt Borgerson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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