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nv2a: Rename PCIDevice dev to parent_obj per QEMU convention

This commit is contained in:
Matt Borgerson 2020-06-17 16:10:03 -07:00 committed by mborgerson
parent 9d75e3cc60
commit f898b5e875
3 changed files with 17 additions and 12 deletions
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8
hw/xbox/nv2a/nv2a.c
View File

@ -93,9 +93,9 @@ static void update_irq(NV2AState *d)
if (d->pmc.pending_interrupts && d->pmc.enabled_interrupts) {
NV2A_DPRINTF("raise irq\n");
pci_irq_assert(&d->dev);
pci_irq_assert(PCI_DEVICE(d));
} else {
pci_irq_deassert(&d->dev);
pci_irq_deassert(PCI_DEVICE(d));
}
}
@ -391,7 +391,7 @@ static void nv2a_init_memory(NV2AState *d, MemoryRegion *ram)
/* PCI exposed vram */
memory_region_init_alias(&d->vram_pci, OBJECT(d), "nv2a-vram-pci", d->vram,
0, memory_region_size(d->vram));
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, &d->vram_pci);
pci_register_bar(PCI_DEVICE(d), 1, PCI_BASE_ADDRESS_MEM_PREFETCH, &d->vram_pci);
/* RAMIN - should be in vram somewhere, but not quite sure where atm */
@ -485,7 +485,7 @@ static void nv2a_realize(PCIDevice *dev, Error **errp)
/* mmio */
memory_region_init(&d->mmio, OBJECT(dev), "nv2a-mmio", 0x1000000);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(PCI_DEVICE(d), 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
for (int i=0; i < ARRAY_SIZE(blocktable); i++) {
if (!blocktable[i].name) continue;

5
hw/xbox/nv2a/nv2a_int.h
View File

@ -270,7 +270,10 @@ typedef struct PGRAPHState {
} PGRAPHState;
typedef struct NV2AState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
qemu_irq irq;
bool exiting;

16
hw/xbox/nv2a/nv2a_pbus.c
View File

@ -3,7 +3,7 @@
*
* Copyright (c) 2012 espes
* Copyright (c) 2015 Jannik Vogel
* Copyright (c) 2018 Matt Borgerson
* Copyright (c) 2018-2020 Matt Borgerson
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@ -22,18 +22,19 @@
/* PBUS - bus control */
uint64_t pbus_read(void *opaque, hwaddr addr, unsigned int size)
{
NV2AState *d = opaque;
NV2AState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
uint64_t r = 0;
switch (addr) {
case NV_PBUS_PCI_NV_0:
r = pci_get_long(d->dev.config + PCI_VENDOR_ID);
r = pci_get_long(d->config + PCI_VENDOR_ID);
break;
case NV_PBUS_PCI_NV_1:
r = pci_get_long(d->dev.config + PCI_COMMAND);
r = pci_get_long(d->config + PCI_COMMAND);
break;
case NV_PBUS_PCI_NV_2:
r = pci_get_long(d->dev.config + PCI_CLASS_REVISION);
r = pci_get_long(d->config + PCI_CLASS_REVISION);
break;
default:
break;
@ -45,13 +46,14 @@ uint64_t pbus_read(void *opaque, hwaddr addr, unsigned int size)
void pbus_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
{
NV2AState *d = opaque;
NV2AState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
reg_log_write(NV_PBUS, addr, val);
switch (addr) {
case NV_PBUS_PCI_NV_1:
pci_set_long(d->dev.config + PCI_COMMAND, val);
pci_set_long(d->config + PCI_COMMAND, val);
break;
default:
break;