From af0b5b7b2a3bd78cd1a01115103c28e2f54d34bc Mon Sep 17 00:00:00 2001 From: Maria Klauchek Date: Mon, 2 Sep 2024 13:34:33 +0300 Subject: [PATCH] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension FCSR is a part of F extension. Print it to log if FPU option is enabled. Signed-off-by: Maria Klauchek Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a1ca12077f..89bc3955ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -823,6 +823,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } if (flags & CPU_DUMP_FPU) { + target_ulong val = 0; + RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0); + if (res == RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[CSR_FCSR].name, val); + } for (i = 0; i < 32; i++) { qemu_fprintf(f, " %-8s %016" PRIx64, riscv_fpr_regnames[i], env->fpr[i]);