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target/i386: tcg: fix loading of registers from 16-bit TSS 

According to the manual, the high 16-bit of the registers are preserved
when switching to a 16-bit task.  Implement this in switch_tss_ra.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2021-06-01 15:34:26 +02:00
parent 28f6aa1178
commit a5505f6b5b
1 changed files with 11 additions and 14 deletions
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25
target/i386/tcg/seg_helper.c
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@ -277,8 +277,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
new_eip = cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr);
new_eflags = cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr);
for (i = 0; i < 8; i++) {
new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2),
retaddr) | 0xffff0000;
new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2), retaddr);
}
for (i = 0; i < 4; i++) {
new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2),
@ -391,19 +390,17 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
env->eip = new_eip;
eflags_mask = TF_MASK | AC_MASK | ID_MASK |
IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
if (!(type & 8)) {
eflags_mask &= 0xffff;
if (type & 8) {
cpu_load_eflags(env, new_eflags, eflags_mask);
for (i = 0; i < 8; i++) {
env->regs[i] = new_regs[i];
}
} else {
cpu_load_eflags(env, new_eflags, eflags_mask & 0xffff);
for (i = 0; i < 8; i++) {
env->regs[i] = (env->regs[i] & 0xffff0000) | new_regs[i];
}
}
cpu_load_eflags(env, new_eflags, eflags_mask);
/* XXX: what to do in 16 bit case? */
env->regs[R_EAX] = new_regs[0];
env->regs[R_ECX] = new_regs[1];
env->regs[R_EDX] = new_regs[2];
env->regs[R_EBX] = new_regs[3];
env->regs[R_ESP] = new_regs[4];
env->regs[R_EBP] = new_regs[5];
env->regs[R_ESI] = new_regs[6];
env->regs[R_EDI] = new_regs[7];
if (new_eflags & VM_MASK) {
for (i = 0; i < 6; i++) {
load_seg_vm(env, i, new_segs[i]);