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target/i386: tcg: fix segment register offsets for 16-bit TSS 

The TSS offsets in the manuals have only 2-byte slots for the
segment registers.  QEMU incorrectly uses 4-byte slots, so
that SS overlaps the LDT selector.

Resolves: 
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2021-06-01 15:31:38 +02:00
parent 29c3d213f4
commit 28f6aa1178
1 changed files with 2 additions and 2 deletions
target/i386/tcg
seg_helper.c

4
target/i386/tcg/seg_helper.c
View File

@ -281,7 +281,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
retaddr) | 0xffff0000;
}
for (i = 0; i < 4; i++) {
new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 4),
new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2),
retaddr);
}
new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr);
@ -349,7 +349,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr);
cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr);
for (i = 0; i < 4; i++) {
cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 4),
cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2),
env->segs[i].selector, retaddr);
}
}