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target/sparc: Move gen_fop_QQQ insns to decodetree
Move FADDq, FSUBq, FMULq, FDIVq. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -250,12 +250,16 @@ FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
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FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
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FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
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FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r
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FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r
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FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
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FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r
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FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r
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FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
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FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r
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FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r
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FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
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FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
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FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r
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FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
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FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
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FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
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@ -1669,19 +1669,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
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}
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#endif
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static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
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void (*gen)(TCGv_ptr))
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{
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gen_op_load_fpr_QT0(QFPREG(rs1));
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gen_op_load_fpr_QT1(QFPREG(rs2));
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gen(tcg_env);
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gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
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gen_op_store_QT0_fpr(QFPREG(rd));
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gen_update_fprs_dirty(dc, QFPREG(rd));
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}
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static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
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void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
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{
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@ -4964,6 +4951,31 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
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TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist)
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static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_env))
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{
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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if (gen_trap_float128(dc)) {
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return true;
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}
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gen_op_clear_ieee_excp_and_FTT();
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gen_op_load_fpr_QT0(QFPREG(a->rs1));
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gen_op_load_fpr_QT1(QFPREG(a->rs2));
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func(tcg_env);
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gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
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gen_op_store_QT0_fpr(QFPREG(a->rd));
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gen_update_fprs_dirty(dc, QFPREG(a->rd));
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return advance_pc(dc);
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}
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TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq)
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TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq)
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TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq)
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TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
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#define CHECK_IU_FEATURE(dc, FEATURE) \
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if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
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goto illegal_insn;
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@ -5025,23 +5037,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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case 0x46: /* fsubd */
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case 0x4a: /* fmuld */
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case 0x4e: /* fdivd */
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g_assert_not_reached(); /* in decodetree */
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case 0x43: /* faddq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
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break;
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case 0x47: /* fsubq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
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break;
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case 0x4b: /* fmulq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
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break;
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case 0x4f: /* fdivq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
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break;
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g_assert_not_reached(); /* in decodetree */
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case 0x69: /* fsmuld */
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CHECK_FPU_FEATURE(dc, FSMULD);
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gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
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