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target/sparc: Move gen_fop_DDD insns to decodetree
Move FADDd, FSUBd, FMULd, FDIVd. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -249,9 +249,13 @@ FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
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FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
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FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
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FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
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FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r
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FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
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FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r
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FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
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FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r
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FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
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FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
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FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
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FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
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FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
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@ -1656,21 +1656,6 @@ static int gen_trap_ifnofpu(DisasContext *dc)
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return 0;
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}
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static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
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void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
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{
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TCGv_i64 dst, src1, src2;
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src1 = gen_load_fpr_D(dc, rs1);
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src2 = gen_load_fpr_D(dc, rs2);
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dst = gen_dest_fpr_D(dc, rd);
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gen(dst, tcg_env, src1, src2);
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gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
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gen_store_fpr_D(dc, rd, dst);
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}
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#ifdef TARGET_SPARC64
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static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
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void (*gen)(TCGv_ptr))
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@ -4935,6 +4920,30 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32)
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TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata)
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TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle)
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static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
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{
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TCGv_i64 dst, src1, src2;
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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gen_op_clear_ieee_excp_and_FTT();
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dst = gen_dest_fpr_D(dc, a->rd);
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src1 = gen_load_fpr_D(dc, a->rs1);
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src2 = gen_load_fpr_D(dc, a->rs2);
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func(dst, tcg_env, src1, src2);
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gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
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gen_store_fpr_D(dc, a->rd, dst);
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return advance_pc(dc);
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}
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TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd)
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TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd)
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TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld)
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TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd)
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static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
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void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
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{
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@ -5012,31 +5021,23 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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case 0x45: /* fsubs */
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case 0x49: /* fmuls */
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case 0x4d: /* fdivs */
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g_assert_not_reached(); /* in decodetree */
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case 0x42: /* faddd */
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gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
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break;
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case 0x46: /* fsubd */
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case 0x4a: /* fmuld */
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case 0x4e: /* fdivd */
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g_assert_not_reached(); /* in decodetree */
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case 0x43: /* faddq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
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break;
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case 0x46: /* fsubd */
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gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
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break;
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case 0x47: /* fsubq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
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break;
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case 0x4a: /* fmuld */
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gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
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break;
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case 0x4b: /* fmulq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
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break;
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case 0x4e: /* fdivd */
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gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
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break;
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case 0x4f: /* fdivq */
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CHECK_FPU_FEATURE(dc, FLOAT128);
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gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
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