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target/sparc: Move gen_fop_DDD insns to decodetree 

Move FADDd, FSUBd, FMULd, FDIVd.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-11 15:51:13 -07:00
parent c1514961e6
commit f2a59b0ad7
2 changed files with 32 additions and 27 deletions
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4
target/sparc/insns.decode
View File

@ -249,9 +249,13 @@ FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r
FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r
FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r
FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2

55
target/sparc/translate.c
View File

@ -1656,21 +1656,6 @@ static int gen_trap_ifnofpu(DisasContext *dc)
return 0;
}
static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
{
TCGv_i64 dst, src1, src2;
src1 = gen_load_fpr_D(dc, rs1);
src2 = gen_load_fpr_D(dc, rs2);
dst = gen_dest_fpr_D(dc, rd);
gen(dst, tcg_env, src1, src2);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, rd, dst);
}
#ifdef TARGET_SPARC64
static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_ptr))
@ -4935,6 +4920,30 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32)
TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata)
TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle)
static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
{
TCGv_i64 dst, src1, src2;
if (gen_trap_ifnofpu(dc)) {
return true;
}
gen_op_clear_ieee_excp_and_FTT();
dst = gen_dest_fpr_D(dc, a->rd);
src1 = gen_load_fpr_D(dc, a->rs1);
src2 = gen_load_fpr_D(dc, a->rs2);
func(dst, tcg_env, src1, src2);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_D(dc, a->rd, dst);
return advance_pc(dc);
}
TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd)
TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd)
TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld)
TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd)
static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
{
@ -5012,31 +5021,23 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x45: /* fsubs */
case 0x49: /* fmuls */
case 0x4d: /* fdivs */
g_assert_not_reached(); /* in decodetree */
case 0x42: /* faddd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
break;
case 0x46: /* fsubd */
case 0x4a: /* fmuld */
case 0x4e: /* fdivd */
g_assert_not_reached(); /* in decodetree */
case 0x43: /* faddq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
break;
case 0x46: /* fsubd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
break;
case 0x47: /* fsubq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
break;
case 0x4a: /* fmuld */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
break;
case 0x4b: /* fmulq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
break;
case 0x4e: /* fdivd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
break;
case 0x4f: /* fdivq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);