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Misc patches queue 

. Remove deprecated pc-i440fx-2.0 -> 2.3 machines (Phil)
 . Always use little endian audio format in virtio-snd (Phil)
 . Avoid using Monitor in INTERRUPT_STATS_PROVIDER::print_info (Phil)
 . Introduce x-query-interrupt-controllers QMP command (Phil)
 . Introduce pnv_chip_foreach_cpu() to remove one CPU_FOREACH use (Cédric)
 . Constify few uses of IOMMUTLBEvent (Phil)
 . Wire loongson_ipi device to loongson3_virt/TCG (Jiaxun)
 . Fix inclusion of tracing headers on s390x/TCG (Phil)
 . Add few shortcuts missing to readline (Manos)
 . Update ui/display entries in MAINTAINERS (Gerd)
 . Use qemu_add_mouse_change_notifier on Cocoa (Akihiko)
 . Fix Standard VGA screen blanking and cleanups (Gerd)
 . Fix USB/MTP reported "free space" value (Fabio)
 . Cast size_memop() returned value (Roman)
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Merge tag 'misc-20240619' of https://github.com/philmd/qemu into staging

Misc patches queue

. Remove deprecated pc-i440fx-2.0 -> 2.3 machines (Phil)
. Always use little endian audio format in virtio-snd (Phil)
. Avoid using Monitor in INTERRUPT_STATS_PROVIDER::print_info (Phil)
. Introduce x-query-interrupt-controllers QMP command (Phil)
. Introduce pnv_chip_foreach_cpu() to remove one CPU_FOREACH use (Cédric)
. Constify few uses of IOMMUTLBEvent (Phil)
. Wire loongson_ipi device to loongson3_virt/TCG (Jiaxun)
. Fix inclusion of tracing headers on s390x/TCG (Phil)
. Add few shortcuts missing to readline (Manos)
. Update ui/display entries in MAINTAINERS (Gerd)
. Use qemu_add_mouse_change_notifier on Cocoa (Akihiko)
. Fix Standard VGA screen blanking and cleanups (Gerd)
. Fix USB/MTP reported "free space" value (Fabio)
. Cast size_memop() returned value (Roman)

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# gpg: Signature made Wed 19 Jun 2024 03:53:26 AM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'misc-20240619' of https://github.com/philmd/qemu: (74 commits)
  exec: Make the MemOp enum cast explicit
  ui+display: rename is_buffer_shared() -> surface_is_allocated()
  ui+display: rename is_placeholder() -> surface_is_placeholder()
  stdvga: fix screen blanking
  ui/cocoa: Use qemu_add_mouse_change_notifier
  MAINTAINERS: drop spice+ui maintainership
  MAINTAINERS: drop virtio-gpu maintainership
  util/readline: Add C-u shortcut
  util/readline: Add C-n, C-p shortcuts
  util/readline: Fix lints for readline_handle_byte
  target/s390x: Use s390_skeys_get|set() helper
  hw/s390x: Introduce s390_skeys_get|set() helpers
  hw/mips/loongson3_virt: Wire up loongson_ipi device
  hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id
  hw/intc/loongson_ipi: Provide per core MMIO address spaces
  hw/intc: Remove loongarch_ipi.c
  hw/usb/dev-mtp: Correctly report free space
  hw/usb: Remove unused 'host.h' header
  hw/i386/iommu: Constify IOMMUTLBEvent in vtd_page_walk_hook prototype
  memory: Constify IOMMUTLBEvent in memory_region_notify_iommu()
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-06-19 10:54:31 -07:00
parent 223696363b fc0870c180
commit 80748eb4fb
91 changed files with 743 additions and 1416 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -2579,8 +2579,7 @@ F: hw/display/ramfb*.c
F: include/hw/display/ramfb.h
virtio-gpu
M: Gerd Hoffmann <kraxel@redhat.com>
S: Odd Fixes
S: Orphan
F: hw/display/virtio-gpu*
F: hw/display/virtio-vga.*
F: include/hw/virtio/virtio-gpu.h
@ -2602,7 +2601,6 @@ F: include/hw/virtio/virtio-blk-common.h
vhost-user-gpu
M: Marc-André Lureau <marcandre.lureau@redhat.com>
R: Gerd Hoffmann <kraxel@redhat.com>
S: Maintained
F: docs/interop/vhost-user-gpu.rst
F: contrib/vhost-user-gpu
@ -3060,8 +3058,7 @@ F: stubs/memory_device.c
F: docs/nvdimm.txt
SPICE
M: Gerd Hoffmann <kraxel@redhat.com>
S: Odd Fixes
S: Orphan
F: include/ui/qemu-spice.h
F: include/ui/spice-display.h
F: ui/spice-*.c
@ -3071,7 +3068,6 @@ F: qapi/ui.json
F: docs/spice-port-fqdn.txt
Graphics
M: Gerd Hoffmann <kraxel@redhat.com>
M: Marc-André Lureau <marcandre.lureau@redhat.com>
S: Odd Fixes
F: ui/

4
docs/about/deprecated.rst
View File

@ -212,8 +212,8 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node.
``pc-i440fx-2.0`` up to ``pc-i440fx-2.3`` (since 8.2)
'''''''''''''''''''''''''''''''''''''''''''''''''''''
``pc-i440fx-2.4`` up to ``pc-i440fx-2.12`` (since 9.1)
''''''''''''''''''''''''''''''''''''''''''''''''''''''
These old machine types are quite neglected nowadays and thus might have
various pitfalls with regards to live migration. Use a newer machine type

2
docs/about/removed-features.rst
View File

@ -948,7 +948,7 @@ mips ``fulong2e`` machine alias (removed in 6.0)
This machine has been renamed ``fuloong2e``.
``pc-0.10`` up to ``pc-i440fx-1.7`` (removed in 4.0 up to 8.2)
``pc-0.10`` up to ``pc-i440fx-2.3`` (removed in 4.0 up to 9.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
These machine types were very old and likely could not be used for live

2
hmp-commands-info.hx
View File

@ -174,7 +174,7 @@ ERST
.args_type = "",
.params = "",
.help = "show PIC state",
.cmd = hmp_info_pic,
.cmd_info_hrt = qmp_x_query_interrupt_controllers,
},
SRST

46
hw/acpi/ich9.c
View File

@ -153,17 +153,10 @@ static int ich9_pm_post_load(void *opaque, int version_id)
.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
}
static bool vmstate_test_use_memhp(void *opaque)
{
ICH9LPCPMRegs *s = opaque;
return s->acpi_memory_hotplug.is_enabled;
}
static const VMStateDescription vmstate_memhp_state = {
.name = "ich9_pm/memhp",
.version_id = 1,
.minimum_version_id = 1,
.needed = vmstate_test_use_memhp,
.fields = (const VMStateField[]) {
VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
VMSTATE_END_OF_LIST()
@ -335,11 +328,9 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
legacy_acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
if (pm->acpi_memory_hotplug.is_enabled) {
acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
&pm->acpi_memory_hotplug,
ACPI_MEMORY_HOTPLUG_BASE);
}
acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
&pm->acpi_memory_hotplug,
ACPI_MEMORY_HOTPLUG_BASE);
}
static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name,
@ -351,21 +342,6 @@ static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v, const char *name,
visit_type_uint32(v, name, &value, errp);
}
static bool ich9_pm_get_memory_hotplug_support(Object *obj, Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
return s->pm.acpi_memory_hotplug.is_enabled;
}
static void ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
s->pm.acpi_memory_hotplug.is_enabled = value;
}
static bool ich9_pm_get_cpu_hotplug_legacy(Object *obj, Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
@ -445,9 +421,6 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm)
NULL, NULL, pm);
object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
&gpe0_len, OBJ_PROP_FLAG_READ);
object_property_add_bool(obj, "memory-hotplug-support",
ich9_pm_get_memory_hotplug_support,
ich9_pm_set_memory_hotplug_support);
object_property_add_bool(obj, "cpu-hotplug-legacy",
ich9_pm_get_cpu_hotplug_legacy,
ich9_pm_set_cpu_hotplug_legacy);
@ -478,12 +451,7 @@ void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
return;
}
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
!lpc->pm.acpi_memory_hotplug.is_enabled) {
error_setg(errp,
"memory hotplug is not enabled: %s.memory-hotplug-support "
"is not set", object_get_typename(OBJECT(lpc)));
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
uint64_t negotiated = lpc->smi_negotiated_features;
if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) &&
@ -527,8 +495,7 @@ void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
if (lpc->pm.acpi_memory_hotplug.is_enabled &&
object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
acpi_memory_unplug_request_cb(hotplug_dev,
&lpc->pm.acpi_memory_hotplug, dev,
errp);
@ -563,8 +530,7 @@ void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
if (lpc->pm.acpi_memory_hotplug.is_enabled &&
object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
acpi_memory_unplug_cb(&lpc->pm.acpi_memory_hotplug, dev, errp);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
!lpc->pm.cpu_hotplug_legacy) {

5
hw/arm/virt.c
View File

@ -1677,8 +1677,7 @@ static void virt_build_smbios(VirtMachineState *vms)
}
smbios_set_defaults("QEMU", product,
vmc->smbios_old_sys_ver ? "1.0" : mc->name,
true);
vmc->smbios_old_sys_ver ? "1.0" : mc->name);
/* build the array of physical mem area from base_memmap */
mem_array.address = vms->memmap[VIRT_MEM].base;
@ -2764,7 +2763,7 @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
return;
}
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
}
static void virt_memory_plug(HotplugHandler *hotplug_dev,

2
hw/audio/virtio-snd.c
View File

@ -401,7 +401,7 @@ static void virtio_snd_get_qemu_audsettings(audsettings *as,
as->nchannels = MIN(AUDIO_MAX_CHANNELS, params->channels);
as->fmt = virtio_snd_get_qemu_format(params->format);
as->freq = virtio_snd_get_qemu_freq(params->rate);
as->endianness = target_words_bigendian() ? 1 : 0;
as->endianness = 0; /* Conforming to VIRTIO 1.0: always little endian. */
}
/*

29
hw/core/machine-qmp-cmds.c
View File

@ -361,6 +361,35 @@ HumanReadableText *qmp_x_query_irq(Error **errp)
return human_readable_text_from_str(buf);
}
static int qmp_x_query_intc_foreach(Object *obj, void *opaque)
{
InterruptStatsProvider *intc;
InterruptStatsProviderClass *k;
GString *buf = opaque;
if (object_dynamic_cast(obj, TYPE_INTERRUPT_STATS_PROVIDER)) {
intc = INTERRUPT_STATS_PROVIDER(obj);
k = INTERRUPT_STATS_PROVIDER_GET_CLASS(obj);
if (k->print_info) {
k->print_info(intc, buf);
} else {
g_string_append_printf(buf,
"Interrupt controller information not available for %s.\n",
object_get_typename(obj));
}
}
return 0;
}
HumanReadableText *qmp_x_query_interrupt_controllers(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
object_child_foreach_recursive(object_get_root(),
qmp_x_query_intc_foreach, buf);
return human_readable_text_from_str(buf);
}
GuidInfo *qmp_query_vm_generation_id(Error **errp)
{
GuidInfo *info;

2
hw/display/qxl-render.c
View File

@ -31,7 +31,7 @@ static void qxl_blit(PCIQXLDevice *qxl, QXLRect *rect)
uint8_t *src;
int len, i;
if (is_buffer_shared(surface)) {
if (!surface_is_allocated(surface)) {
return;
}
trace_qxl_render_blit(qxl->guest_primary.qxl_stride,

25
hw/display/vga.c
View File

@ -1487,7 +1487,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
uint8_t *d;
uint32_t v, addr1, addr;
vga_draw_line_func *vga_draw_line = NULL;
bool share_surface, force_shadow = false;
bool allocate_surface, force_shadow = false;
pixman_format_code_t format;
#if HOST_BIG_ENDIAN
bool byteswap = !s->big_endian_fb;
@ -1609,10 +1609,10 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
*/
format = qemu_default_pixman_format(depth, !byteswap);
if (format) {
share_surface = dpy_gfx_check_format(s->con, format)
&& !s->force_shadow && !force_shadow;
allocate_surface = !dpy_gfx_check_format(s->con, format)
|| s->force_shadow || force_shadow;
} else {
share_surface = false;
allocate_surface = true;
}
if (s->params.line_offset != s->last_line_offset ||
@ -1620,7 +1620,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
height != s->last_height ||
s->last_depth != depth ||
s->last_byteswap != byteswap ||
share_surface != is_buffer_shared(surface)) {
allocate_surface != surface_is_allocated(surface)) {
/* display parameters changed -> need new display surface */
s->last_scr_width = disp_width;
s->last_scr_height = height;
@ -1635,14 +1635,14 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
full_update = 1;
}
if (surface_data(surface) != s->vram_ptr + (s->params.start_addr * 4)
&& is_buffer_shared(surface)) {
&& !surface_is_allocated(surface)) {
/* base address changed (page flip) -> shared display surfaces
* must be updated with the new base address */
full_update = 1;
}
if (full_update) {
if (share_surface) {
if (!allocate_surface) {
surface = qemu_create_displaysurface_from(disp_width,
height, format, s->params.line_offset,
s->vram_ptr + (s->params.start_addr * 4));
@ -1655,7 +1655,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
vga_draw_line = vga_draw_line_table[v];
if (!is_buffer_shared(surface) && s->cursor_invalidate) {
if (surface_is_allocated(surface) && s->cursor_invalidate) {
s->cursor_invalidate(s);
}
@ -1707,7 +1707,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
if (update) {
if (y_start < 0)
y_start = y;
if (!(is_buffer_shared(surface))) {
if (surface_is_allocated(surface)) {
uint8_t *p;
p = vga_draw_line(s, d, addr, width, hpel);
if (p) {
@ -1762,6 +1762,13 @@ static void vga_draw_blank(VGACommonState *s, int full_update)
if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
return;
if (!surface_is_allocated(surface)) {
/* unshare buffer, otherwise the blanking corrupts vga vram */
surface = qemu_create_displaysurface(s->last_scr_width,
s->last_scr_height);
dpy_gfx_replace_surface(s->con, surface);
}
w = s->last_scr_width * surface_bytes_per_pixel(surface);
d = surface_data(surface);
for(i = 0; i < s->last_scr_height; i++) {

5
hw/display/xenfb.c
View File

@ -638,7 +638,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h)
int linesize = surface_stride(surface);
uint8_t *data = surface_data(surface);
if (!is_buffer_shared(surface)) {
if (surface_is_allocated(surface)) {
switch (xenfb->depth) {
case 8:
if (bpp == 16) {
@ -756,7 +756,8 @@ static void xenfb_update(void *opaque)
xen_pv_printf(&xenfb->c.xendev, 1,
"update: resizing: %dx%d @ %d bpp%s\n",
xenfb->width, xenfb->height, xenfb->depth,
is_buffer_shared(surface) ? " (shared)" : "");
surface_is_allocated(surface)
? " (allocated)" : " (borrowed)");
xenfb->up_fullscreen = 1;
}

96
hw/i386/acpi-build.c
View File

@ -85,7 +85,6 @@
* a little bit, there should be plenty of free space since the DSDT
* shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
*/
#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
#define ACPI_BUILD_ALIGN_SIZE 0x1000
#define ACPI_BUILD_TABLE_SIZE 0x20000
@ -2459,7 +2458,6 @@ struct AcpiBuildState {
MemoryRegion *table_mr;
/* Is table patched? */
uint8_t patched;
void *rsdp;
MemoryRegion *rsdp_mr;
MemoryRegion *linker_mr;
} AcpiBuildState;
@ -2495,17 +2493,15 @@ static
void acpi_build(AcpiBuildTables *tables, MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(machine);
DeviceState *iommu = pcms->iommu;
GArray *table_offsets;
unsigned facs, dsdt, rsdt, fadt;
unsigned facs, dsdt, rsdt;
AcpiPmInfo pm;
AcpiMiscInfo misc;
AcpiMcfgInfo mcfg;
Range pci_hole = {}, pci_hole64 = {};
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
Object *vmgenid_dev;
@ -2551,19 +2547,12 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
build_dsdt(tables_blob, tables->linker, &pm, &misc,
&pci_hole, &pci_hole64, machine);
/* Count the size of the DSDT and SSDT, we will need it for legacy
* sizing of ACPI tables.
*/
aml_len += tables_blob->len - dsdt;
/* ACPI tables pointed to by RSDT */
fadt = tables_blob->len;
acpi_add_table(table_offsets, tables_blob);
pm.fadt.facs_tbl_offset = &facs;
pm.fadt.dsdt_tbl_offset = &dsdt;
pm.fadt.xdsdt_tbl_offset = &dsdt;
build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
aml_len += tables_blob->len - fadt;
acpi_add_table(table_offsets, tables_blob);
acpi_build_madt(tables_blob, tables->linker, x86ms,
@ -2675,16 +2664,6 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
.rsdt_tbl_offset = &rsdt,
};
build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
if (!pcmc->rsdp_in_ram) {
/* We used to allocate some extra space for RSDP revision 2 but
* only used the RSDP revision 0 space. The extra bytes were
* zeroed out and not used.
* Here we continue wasting those extra 16 bytes to make sure we
* don't break migration for machine types 2.2 and older due to
* RSDP blob size mismatch.
*/
build_append_int_noprefix(tables->rsdp, 0, 16);
}
}
/* We'll expose it all to Guest so we want to reduce
@ -2694,49 +2673,9 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
* too simple to be enough. 4k turned out to be too small an
* alignment very soon, and in fact it is almost impossible to
* keep the table size stable for all (max_cpus, max_memory_slots)
* combinations. So the table size is always 64k for pc-i440fx-2.1
* and we give an error if the table grows beyond that limit.
*
* We still have the problem of migrating from "-M pc-i440fx-2.0". For
* that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
* than 2.0 and we can always pad the smaller tables with zeros. We can
* then use the exact size of the 2.0 tables.
*
* All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
* combinations.
*/
if (pcmc->legacy_acpi_table_size) {
/* Subtracting aml_len gives the size of fixed tables. Then add the
* size of the PIIX4 DSDT/SSDT in QEMU 2.0.
*/
int legacy_aml_len =
pcmc->legacy_acpi_table_size +
ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
int legacy_table_size =
ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
ACPI_BUILD_ALIGN_SIZE);
if ((tables_blob->len > legacy_table_size) &&
!pcmc->resizable_acpi_blob) {
/* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
warn_report("ACPI table size %u exceeds %d bytes,"
" migration may not work",
tables_blob->len, legacy_table_size);
error_printf("Try removing CPUs, NUMA nodes, memory slots"
" or PCI bridges.\n");
}
g_array_set_size(tables_blob, legacy_table_size);
} else {
/* Make sure we have a buffer in case we need to resize the tables. */
if ((tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) &&
!pcmc->resizable_acpi_blob) {
/* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
warn_report("ACPI table size %u exceeds %d bytes,"
" migration may not work",
tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
error_printf("Try removing CPUs, NUMA nodes, memory slots"
" or PCI bridges.\n");
}
acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
}
acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
@ -2774,11 +2713,7 @@ static void acpi_build_update(void *build_opaque)
acpi_ram_update(build_state->table_mr, tables.table_data);
if (build_state->rsdp) {
memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
} else {
acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
}
acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
acpi_build_tables_cleanup(&tables, true);
@ -2803,7 +2738,6 @@ static const VMStateDescription vmstate_acpi_build = {
void acpi_setup(void)
{
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
AcpiBuildTables tables;
AcpiBuildState *build_state;
@ -2865,25 +2799,9 @@ void acpi_setup(void)
tables.vmgenid);
}
if (!pcmc->rsdp_in_ram) {
/*
* Keep for compatibility with old machine types.
* Though RSDP is small, its contents isn't immutable, so
* we'll update it along with the rest of tables on guest access.
*/
uint32_t rsdp_size = acpi_data_len(tables.rsdp);
build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
acpi_build_update, NULL, build_state,
build_state->rsdp, rsdp_size, true);
build_state->rsdp_mr = NULL;
} else {
build_state->rsdp = NULL;
build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE);
}
build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE);
qemu_register_reset(acpi_build_reset, build_state);
acpi_build_reset(build_state);

3
hw/i386/fw_cfg.c
View File

@ -63,8 +63,7 @@ void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState *fw_cfg,
if (pcmc->smbios_defaults) {
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", mc->desc, mc->name,
pcmc->smbios_uuid_encoded);
smbios_set_defaults("QEMU", mc->desc, mc->name);
}
/* tell smbios about cpuid version and features */

8
hw/i386/intel_iommu.c
View File

@ -1170,7 +1170,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce,
}
}
typedef int (*vtd_page_walk_hook)(IOMMUTLBEvent *event, void *private);
typedef int (*vtd_page_walk_hook)(const IOMMUTLBEvent *event, void *private);
/**
* Constant information used during page walking
@ -1533,7 +1533,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
return 0;
}
static int vtd_sync_shadow_page_hook(IOMMUTLBEvent *event,
static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event,
void *private)
{
memory_region_notify_iommu(private, 0, *event);
@ -2219,7 +2219,7 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
* page tables. We just deliver the PSI down to
* invalidate caches.
*/
IOMMUTLBEvent event = {
const IOMMUTLBEvent event = {
.type = IOMMU_NOTIFIER_UNMAP,
.entry = {
.target_as = &address_space_memory,
@ -3889,7 +3889,7 @@ static void vtd_address_space_refresh_all(IntelIOMMUState *s)
vtd_switch_address_space_all(s);
}
static int vtd_replay_hook(IOMMUTLBEvent *event, void *private)
static int vtd_replay_hook(const IOMMUTLBEvent *event, void *private)
{
memory_region_notify_iommu_one(private, event);
return 0;

107
hw/i386/pc.c
View File

@ -265,75 +265,15 @@ GlobalProperty pc_compat_2_4[] = {
};
const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
GlobalProperty pc_compat_2_3[] = {
PC_CPU_MODEL_IDS("2.3.0")
{ TYPE_X86_CPU, "arat", "off" },
{ "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
{ "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
{ "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
{ "n270" "-" TYPE_X86_CPU, "min-level", "5" },
{ "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
{ "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
{ "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
{ "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
};
const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
GlobalProperty pc_compat_2_2[] = {
PC_CPU_MODEL_IDS("2.2.0")
{ "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
{ "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
{ "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
{ "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
{ "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
{ "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
{ "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
};
const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
GlobalProperty pc_compat_2_1[] = {
PC_CPU_MODEL_IDS("2.1.0")
{ "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
{ "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
};
const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
GlobalProperty pc_compat_2_0[] = {
PC_CPU_MODEL_IDS("2.0.0")
{ "virtio-scsi-pci", "any_layout", "off" },
{ "PIIX4_PM", "memory-hotplug-support", "off" },
{ "apic", "version", "0x11" },
{ "nec-usb-xhci", "superspeed-ports-first", "off" },
{ "nec-usb-xhci", "force-pcie-endcap", "on" },
{ "pci-serial", "prog_if", "0" },
{ "pci-serial-2x", "prog_if", "0" },
{ "pci-serial-4x", "prog_if", "0" },
{ "virtio-net-pci", "guest_announce", "off" },
{ "ICH9-LPC", "memory-hotplug-support", "off" },
};
const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
/*
* @PC_FW_DATA:
* Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
* and other BIOS datastructures.
*
* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K
* reported to be used at the moment, 32K should be enough for a while.
*/
#define PC_FW_DATA (0x20000 + 0x8000)
GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
{
@ -716,8 +656,7 @@ void xen_load_linux(PCMachineState *pcms)
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
rom_set_fw(fw_cfg);
x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
pcmc->pvh_enabled);
x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
for (i = 0; i < nb_option_roms; i++) {
assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
!strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
@ -750,7 +689,6 @@ static void pc_get_device_memory_range(PCMachineState *pcms,
hwaddr *base,
ram_addr_t *device_mem_size)
{
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
MachineState *machine = MACHINE(pcms);
ram_addr_t size;
hwaddr addr;
@ -758,10 +696,8 @@ static void pc_get_device_memory_range(PCMachineState *pcms,
size = machine->maxram_size - machine->ram_size;
addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
if (pcmc->enforce_aligned_dimm) {
/* size device region assuming 1G page max alignment per slot */
size += (1 * GiB) * machine->ram_slots;
}
/* size device region assuming 1G page max alignment per slot */
size += (1 * GiB) * machine->ram_slots;
*base = addr;
*device_mem_size = size;
@ -1059,8 +995,7 @@ void pc_memory_init(PCMachineState *pcms,
}
if (linux_boot) {
x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
pcmc->pvh_enabled);
x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
}
for (i = 0; i < nb_option_roms; i++) {
@ -1325,12 +1260,9 @@ void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
const MachineState *ms = MACHINE(hotplug_dev);
const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
const uint64_t legacy_align = TARGET_PAGE_SIZE;
Error *local_err = NULL;
/*
@ -1355,8 +1287,7 @@ static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
return;
}
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
}
static void pc_memory_plug(HotplugHandler *hotplug_dev,
@ -1424,8 +1355,7 @@ static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
{
/* The vmbus handler has no hotplug handler; we should never end up here. */
g_assert(!dev->hotplugged);
memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
errp);
memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp);
}
static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
@ -1816,20 +1746,13 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
pcmc->pci_enabled = true;
pcmc->has_acpi_build = true;
pcmc->rsdp_in_ram = true;
pcmc->smbios_defaults = true;
pcmc->smbios_uuid_encoded = true;
pcmc->gigabyte_align = true;
pcmc->has_reserved_memory = true;
pcmc->enforce_aligned_dimm = true;
pcmc->enforce_amd_1tb_hole = true;
pcmc->isa_bios_alias = true;
/* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
* to be used at the moment, 32K should be enough for a while. */
pcmc->acpi_data_size = 0x20000 + 0x8000;
pcmc->pvh_enabled = true;
pcmc->kvmclock_create_always = true;
pcmc->resizable_acpi_blob = true;
x86mc->apic_xrupt_override = true;
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = pc_get_hotplug_handler;

171
hw/i386/pc_piix.c
View File

@ -66,7 +66,6 @@
#include "hw/hyperv/vmbus-bridge.h"
#include "hw/mem/nvdimm.h"
#include "hw/i386/acpi-build.h"
#include "kvm/kvm-cpu.h"
#include "target/i386/cpu.h"
#define XEN_IOAPIC_NUM_PIRQS 128ULL
@ -415,37 +414,6 @@ static void pc_set_south_bridge(Object *obj, int value, Error **errp)
pcms->south_bridge = PCSouthBridgeOption_lookup.array[value];
}
/* Looking for a pc_compat_2_4() function? It doesn't exist.
* pc_compat_*() functions that run on machine-init time and
* change global QEMU state are deprecated. Please don't create
* one, and implement any pc-*-2.4 (and newer) compat code in
* hw_compat_*, pc_compat_*, or * pc_*_machine_options().
*/
static void pc_compat_2_3_fn(MachineState *machine)
{
X86MachineState *x86ms = X86_MACHINE(machine);
if (kvm_enabled()) {
x86ms->smm = ON_OFF_AUTO_OFF;
}
}
static void pc_compat_2_2_fn(MachineState *machine)
{
pc_compat_2_3_fn(machine);
}
static void pc_compat_2_1_fn(MachineState *machine)
{
pc_compat_2_2_fn(machine);
x86_cpu_change_kvm_default("svm", NULL);
}
static void pc_compat_2_0_fn(MachineState *machine)
{
pc_compat_2_1_fn(machine);
}
#ifdef CONFIG_ISAPC
static void pc_init_isa(MachineState *machine)
{
@ -477,13 +445,9 @@ static void pc_xen_hvm_init(MachineState *machine)
}
#endif
#define DEFINE_I440FX_MACHINE(suffix, name, compatfn, optionfn) \
#define DEFINE_I440FX_MACHINE(suffix, name, optionfn) \
static void pc_init_##suffix(MachineState *machine) \
{ \
void (*compat)(MachineState *m) = (compatfn); \
if (compat) { \
compat(machine); \
} \
pc_init1(machine, TYPE_I440FX_PCI_DEVICE); \
} \
DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
@ -521,7 +485,7 @@ static void pc_i440fx_9_1_machine_options(MachineClass *m)
m->is_default = true;
}
DEFINE_I440FX_MACHINE(v9_1, "pc-i440fx-9.1", NULL,
DEFINE_I440FX_MACHINE(v9_1, "pc-i440fx-9.1",
pc_i440fx_9_1_machine_options);
static void pc_i440fx_9_0_machine_options(MachineClass *m)
@ -537,7 +501,7 @@ static void pc_i440fx_9_0_machine_options(MachineClass *m)
pcmc->isa_bios_alias = false;
}
DEFINE_I440FX_MACHINE(v9_0, "pc-i440fx-9.0", NULL,
DEFINE_I440FX_MACHINE(v9_0, "pc-i440fx-9.0",
pc_i440fx_9_0_machine_options);
static void pc_i440fx_8_2_machine_options(MachineClass *m)
@ -552,7 +516,7 @@ static void pc_i440fx_8_2_machine_options(MachineClass *m)
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
}
DEFINE_I440FX_MACHINE(v8_2, "pc-i440fx-8.2", NULL,
DEFINE_I440FX_MACHINE(v8_2, "pc-i440fx-8.2",
pc_i440fx_8_2_machine_options);
static void pc_i440fx_8_1_machine_options(MachineClass *m)
@ -566,7 +530,7 @@ static void pc_i440fx_8_1_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_8_1, pc_compat_8_1_len);
}
DEFINE_I440FX_MACHINE(v8_1, "pc-i440fx-8.1", NULL,
DEFINE_I440FX_MACHINE(v8_1, "pc-i440fx-8.1",
pc_i440fx_8_1_machine_options);
static void pc_i440fx_8_0_machine_options(MachineClass *m)
@ -581,7 +545,7 @@ static void pc_i440fx_8_0_machine_options(MachineClass *m)
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32;
}
DEFINE_I440FX_MACHINE(v8_0, "pc-i440fx-8.0", NULL,
DEFINE_I440FX_MACHINE(v8_0, "pc-i440fx-8.0",
pc_i440fx_8_0_machine_options);
static void pc_i440fx_7_2_machine_options(MachineClass *m)
@ -591,7 +555,7 @@ static void pc_i440fx_7_2_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
}
DEFINE_I440FX_MACHINE(v7_2, "pc-i440fx-7.2", NULL,
DEFINE_I440FX_MACHINE(v7_2, "pc-i440fx-7.2",
pc_i440fx_7_2_machine_options);
static void pc_i440fx_7_1_machine_options(MachineClass *m)
@ -601,7 +565,7 @@ static void pc_i440fx_7_1_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
}
DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL,
DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1",
pc_i440fx_7_1_machine_options);
static void pc_i440fx_7_0_machine_options(MachineClass *m)
@ -613,7 +577,7 @@ static void pc_i440fx_7_0_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
}
DEFINE_I440FX_MACHINE(v7_0, "pc-i440fx-7.0", NULL,
DEFINE_I440FX_MACHINE(v7_0, "pc-i440fx-7.0",
pc_i440fx_7_0_machine_options);
static void pc_i440fx_6_2_machine_options(MachineClass *m)
@ -623,7 +587,7 @@ static void pc_i440fx_6_2_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
}
DEFINE_I440FX_MACHINE(v6_2, "pc-i440fx-6.2", NULL,
DEFINE_I440FX_MACHINE(v6_2, "pc-i440fx-6.2",
pc_i440fx_6_2_machine_options);
static void pc_i440fx_6_1_machine_options(MachineClass *m)
@ -634,7 +598,7 @@ static void pc_i440fx_6_1_machine_options(MachineClass *m)
m->smp_props.prefer_sockets = true;
}
DEFINE_I440FX_MACHINE(v6_1, "pc-i440fx-6.1", NULL,
DEFINE_I440FX_MACHINE(v6_1, "pc-i440fx-6.1",
pc_i440fx_6_1_machine_options);
static void pc_i440fx_6_0_machine_options(MachineClass *m)
@ -644,7 +608,7 @@ static void pc_i440fx_6_0_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
}
DEFINE_I440FX_MACHINE(v6_0, "pc-i440fx-6.0", NULL,
DEFINE_I440FX_MACHINE(v6_0, "pc-i440fx-6.0",
pc_i440fx_6_0_machine_options);
static void pc_i440fx_5_2_machine_options(MachineClass *m)
@ -654,7 +618,7 @@ static void pc_i440fx_5_2_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
}
DEFINE_I440FX_MACHINE(v5_2, "pc-i440fx-5.2", NULL,
DEFINE_I440FX_MACHINE(v5_2, "pc-i440fx-5.2",
pc_i440fx_5_2_machine_options);
static void pc_i440fx_5_1_machine_options(MachineClass *m)
@ -668,7 +632,7 @@ static void pc_i440fx_5_1_machine_options(MachineClass *m)
pcmc->pci_root_uid = 1;
}
DEFINE_I440FX_MACHINE(v5_1, "pc-i440fx-5.1", NULL,
DEFINE_I440FX_MACHINE(v5_1, "pc-i440fx-5.1",
pc_i440fx_5_1_machine_options);
static void pc_i440fx_5_0_machine_options(MachineClass *m)
@ -680,7 +644,7 @@ static void pc_i440fx_5_0_machine_options(MachineClass *m)
m->auto_enable_numa_with_memdev = false;
}
DEFINE_I440FX_MACHINE(v5_0, "pc-i440fx-5.0", NULL,
DEFINE_I440FX_MACHINE(v5_0, "pc-i440fx-5.0",
pc_i440fx_5_0_machine_options);
static void pc_i440fx_4_2_machine_options(MachineClass *m)
@ -690,7 +654,7 @@ static void pc_i440fx_4_2_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
}
DEFINE_I440FX_MACHINE(v4_2, "pc-i440fx-4.2", NULL,
DEFINE_I440FX_MACHINE(v4_2, "pc-i440fx-4.2",
pc_i440fx_4_2_machine_options);
static void pc_i440fx_4_1_machine_options(MachineClass *m)
@ -700,7 +664,7 @@ static void pc_i440fx_4_1_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
}
DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1",
pc_i440fx_4_1_machine_options);
static void pc_i440fx_4_0_machine_options(MachineClass *m)
@ -712,7 +676,7 @@ static void pc_i440fx_4_0_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
}
DEFINE_I440FX_MACHINE(v4_0, "pc-i440fx-4.0", NULL,
DEFINE_I440FX_MACHINE(v4_0, "pc-i440fx-4.0",
pc_i440fx_4_0_machine_options);
static void pc_i440fx_3_1_machine_options(MachineClass *m)
@ -726,7 +690,7 @@ static void pc_i440fx_3_1_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
}
DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL,
DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1",
pc_i440fx_3_1_machine_options);
static void pc_i440fx_3_0_machine_options(MachineClass *m)
@ -736,17 +700,18 @@ static void pc_i440fx_3_0_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
}
DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL,
DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0",
pc_i440fx_3_0_machine_options);
static void pc_i440fx_2_12_machine_options(MachineClass *m)
{
pc_i440fx_3_0_machine_options(m);
m->deprecation_reason = "old and unattended - use a newer version instead";
compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
}
DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL,
DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12",
pc_i440fx_2_12_machine_options);
static void pc_i440fx_2_11_machine_options(MachineClass *m)
@ -756,7 +721,7 @@ static void pc_i440fx_2_11_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
}
DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11", NULL,
DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11",
pc_i440fx_2_11_machine_options);
static void pc_i440fx_2_10_machine_options(MachineClass *m)
@ -767,7 +732,7 @@ static void pc_i440fx_2_10_machine_options(MachineClass *m)
m->auto_enable_numa_with_memhp = false;
}
DEFINE_I440FX_MACHINE(v2_10, "pc-i440fx-2.10", NULL,
DEFINE_I440FX_MACHINE(v2_10, "pc-i440fx-2.10",
pc_i440fx_2_10_machine_options);
static void pc_i440fx_2_9_machine_options(MachineClass *m)
@ -777,7 +742,7 @@ static void pc_i440fx_2_9_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
}
DEFINE_I440FX_MACHINE(v2_9, "pc-i440fx-2.9", NULL,
DEFINE_I440FX_MACHINE(v2_9, "pc-i440fx-2.9",
pc_i440fx_2_9_machine_options);
static void pc_i440fx_2_8_machine_options(MachineClass *m)
@ -787,7 +752,7 @@ static void pc_i440fx_2_8_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
}
DEFINE_I440FX_MACHINE(v2_8, "pc-i440fx-2.8", NULL,
DEFINE_I440FX_MACHINE(v2_8, "pc-i440fx-2.8",
pc_i440fx_2_8_machine_options);
static void pc_i440fx_2_7_machine_options(MachineClass *m)
@ -797,7 +762,7 @@ static void pc_i440fx_2_7_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
}
DEFINE_I440FX_MACHINE(v2_7, "pc-i440fx-2.7", NULL,
DEFINE_I440FX_MACHINE(v2_7, "pc-i440fx-2.7",
pc_i440fx_2_7_machine_options);
static void pc_i440fx_2_6_machine_options(MachineClass *m)
@ -812,7 +777,7 @@ static void pc_i440fx_2_6_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
}
DEFINE_I440FX_MACHINE(v2_6, "pc-i440fx-2.6", NULL,
DEFINE_I440FX_MACHINE(v2_6, "pc-i440fx-2.6",
pc_i440fx_2_6_machine_options);
static void pc_i440fx_2_5_machine_options(MachineClass *m)
@ -826,7 +791,7 @@ static void pc_i440fx_2_5_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
}
DEFINE_I440FX_MACHINE(v2_5, "pc-i440fx-2.5", NULL,
DEFINE_I440FX_MACHINE(v2_5, "pc-i440fx-2.5",
pc_i440fx_2_5_machine_options);
static void pc_i440fx_2_4_machine_options(MachineClass *m)
@ -840,85 +805,9 @@ static void pc_i440fx_2_4_machine_options(MachineClass *m)
compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
}
DEFINE_I440FX_MACHINE(v2_4, "pc-i440fx-2.4", NULL,
DEFINE_I440FX_MACHINE(v2_4, "pc-i440fx-2.4",
pc_i440fx_2_4_machine_options)
static void pc_i440fx_2_3_machine_options(MachineClass *m)
{
pc_i440fx_2_4_machine_options(m);
m->hw_version = "2.3.0";
m->deprecation_reason = "old and unattended - use a newer version instead";
compat_props_add(m->compat_props, hw_compat_2_3, hw_compat_2_3_len);
compat_props_add(m->compat_props, pc_compat_2_3, pc_compat_2_3_len);
}
DEFINE_I440FX_MACHINE(v2_3, "pc-i440fx-2.3", pc_compat_2_3_fn,
pc_i440fx_2_3_machine_options);
static void pc_i440fx_2_2_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_3_machine_options(m);
m->hw_version = "2.2.0";
m->default_machine_opts = "firmware=bios-256k.bin,suppress-vmdesc=on";
compat_props_add(m->compat_props, hw_compat_2_2, hw_compat_2_2_len);
compat_props_add(m->compat_props, pc_compat_2_2, pc_compat_2_2_len);
pcmc->rsdp_in_ram = false;
pcmc->resizable_acpi_blob = false;
}
DEFINE_I440FX_MACHINE(v2_2, "pc-i440fx-2.2", pc_compat_2_2_fn,
pc_i440fx_2_2_machine_options);
static void pc_i440fx_2_1_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_2_machine_options(m);
m->hw_version = "2.1.0";
m->default_display = NULL;
compat_props_add(m->compat_props, hw_compat_2_1, hw_compat_2_1_len);
compat_props_add(m->compat_props, pc_compat_2_1, pc_compat_2_1_len);
pcmc->smbios_uuid_encoded = false;
pcmc->enforce_aligned_dimm = false;
}
DEFINE_I440FX_MACHINE(v2_1, "pc-i440fx-2.1", pc_compat_2_1_fn,
pc_i440fx_2_1_machine_options);
static void pc_i440fx_2_0_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_2_1_machine_options(m);
m->hw_version = "2.0.0";
compat_props_add(m->compat_props, pc_compat_2_0, pc_compat_2_0_len);
pcmc->smbios_legacy_mode = true;
pcmc->has_reserved_memory = false;
/* This value depends on the actual DSDT and SSDT compiled into
* the source QEMU; unfortunately it depends on the binary and
* not on the machine type, so we cannot make pc-i440fx-1.7 work on
* both QEMU 1.7 and QEMU 2.0.
*
* Large variations cause migration to fail for more than one
* consecutive value of the "-smp" maxcpus option.
*
* For small variations of the kind caused by different iasl versions,
* the 4k rounding usually leaves slack. However, there could be still
* one or two values that break. For QEMU 1.7 and QEMU 2.0 the
* slack is only ~10 bytes before one "-smp maxcpus" value breaks!
*
* 6652 is valid for QEMU 2.0, the right value for pc-i440fx-1.7 on
* QEMU 1.7 it is 6414. For RHEL/CentOS 7.0 it is 6418.
*/
pcmc->legacy_acpi_table_size = 6652;
pcmc->acpi_data_size = 0x10000;
}
DEFINE_I440FX_MACHINE(v2_0, "pc-i440fx-2.0", pc_compat_2_0_fn,
pc_i440fx_2_0_machine_options);
#ifdef CONFIG_ISAPC
static void isapc_machine_options(MachineClass *m)
{

8
hw/intc/goldfish_pic.c
View File

@ -12,7 +12,6 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "qemu/log.h"
#include "trace.h"
#include "hw/intc/intc.h"
@ -39,11 +38,12 @@ static bool goldfish_pic_get_statistics(InterruptStatsProvider *obj,
return true;
}
static void goldfish_pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void goldfish_pic_print_info(InterruptStatsProvider *obj, GString *buf)
{
GoldfishPICState *s = GOLDFISH_PIC(obj);
monitor_printf(mon, "goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n",
s->idx, s->pending, s->enabled);
g_string_append_printf(buf,
"goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n",
s->idx, s->pending, s->enabled);
}
static void goldfish_pic_update(GoldfishPICState *s)

14
hw/intc/i8259_common.c
View File

@ -28,7 +28,6 @@
#include "hw/isa/i8259_internal.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "qapi/error.h"
static int irq_level[16];
@ -132,16 +131,17 @@ static bool pic_get_statistics(InterruptStatsProvider *obj,
return true;
}
static void pic_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void pic_print_info(InterruptStatsProvider *obj, GString *buf)
{
PICCommonState *s = PIC_COMMON(obj);
pic_dispatch_pre_save(s);
monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add,
s->irq_base, s->read_reg_select, s->elcr,
s->special_fully_nested_mode);
g_string_append_printf(buf, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
s->master ? 0 : 1, s->irr, s->imr, s->isr,
s->priority_add,
s->irq_base, s->read_reg_select, s->elcr,
s->special_fully_nested_mode);
}
static bool ltim_state_needed(void *opaque)

57
hw/intc/ioapic_common.c
View File

@ -23,7 +23,6 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
@ -59,59 +58,62 @@ static bool ioapic_get_statistics(InterruptStatsProvider *obj,
return true;
}
static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap)
static void ioapic_irr_dump(GString *buf, const char *name, uint32_t bitmap)
{
int i;
monitor_printf(mon, "%-10s ", name);
g_string_append_printf(buf, "%-10s ", name);
if (bitmap == 0) {
monitor_printf(mon, "(none)\n");
g_string_append_printf(buf, "(none)\n");
return;
}
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
if (bitmap & (1 << i)) {
monitor_printf(mon, "%-2u ", i);
g_string_append_printf(buf, "%-2u ", i);
}
}
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
static void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s)
static void ioapic_print_redtbl(GString *buf, IOAPICCommonState *s)
{
static const char *delm_str[] = {
"fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"};
uint32_t remote_irr = 0;
int i;
monitor_printf(mon, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x",
s->version, s->id, s->ioregsel);
g_string_append_printf(buf, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x",
s->version, s->id, s->ioregsel);
if (s->ioregsel) {
monitor_printf(mon, " (redir[%u])\n",
(s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1);
g_string_append_printf(buf, " (redir[%u])\n",
(s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1);
} else {
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
uint64_t entry = s->ioredtbl[i];
uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >>
IOAPIC_LVT_DELIV_MODE_SHIFT);
monitor_printf(mon, " pin %-2u 0x%016"PRIx64" dest=%"PRIx64
" vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n",
i, entry,
(entry >> IOAPIC_LVT_DEST_SHIFT) &
(entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf),
entry & IOAPIC_VECTOR_MASK,
entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi",
entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge",
entry & IOAPIC_LVT_MASKED ? "masked" : "",
delm_str[delm],
entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical");
g_string_append_printf(buf, " pin %-2u 0x%016"PRIx64" dest=%"PRIx64
" vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n",
i, entry,
(entry >> IOAPIC_LVT_DEST_SHIFT) &
(entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf),
entry & IOAPIC_VECTOR_MASK,
entry & IOAPIC_LVT_POLARITY
? "active-lo" : "active-hi",
entry & IOAPIC_LVT_TRIGGER_MODE
? "level" : "edge",
entry & IOAPIC_LVT_MASKED ? "masked" : "",
delm_str[delm],
entry & IOAPIC_LVT_DEST_MODE
? "logical" : "physical");
remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ?
(entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0;
}
ioapic_irr_dump(mon, " IRR", s->irr);
ioapic_irr_dump(mon, " Remote IRR", remote_irr);
ioapic_irr_dump(buf, " IRR", s->irr);
ioapic_irr_dump(buf, " Remote IRR", remote_irr);
}
void ioapic_reset_common(DeviceState *dev)
@ -171,13 +173,12 @@ static void ioapic_common_realize(DeviceState *dev, Error **errp)
ioapic_no++;
}
static void ioapic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
static void ioapic_print_info(InterruptStatsProvider *obj, GString *buf)
{
IOAPICCommonState *s = IOAPIC_COMMON(obj);
ioapic_dispatch_pre_save(s);
ioapic_print_redtbl(mon, s);
ioapic_print_redtbl(buf, s);
}
static const VMStateDescription vmstate_ioapic_common = {

347
hw/intc/loongarch_ipi.c
View File

@ -1,347 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* LoongArch ipi interrupt support
*
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#include "qemu/osdep.h"
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
#include "migration/vmstate.h"
#include "target/loongarch/cpu.h"
#include "trace.h"
static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
IPICore *s;
LoongArchIPI *ipi = opaque;
uint64_t ret = 0;
int index = 0;
s = &ipi->cpu[attrs.requester_id];
addr &= 0xff;
switch (addr) {
case CORE_STATUS_OFF:
ret = s->status;
break;
case CORE_EN_OFF:
ret = s->en;
break;
case CORE_SET_OFF:
ret = 0;
break;
case CORE_CLEAR_OFF:
ret = 0;
break;
case CORE_BUF_20 ... CORE_BUF_38 + 4:
index = (addr - CORE_BUF_20) >> 2;
ret = s->buf[index];
break;
default:
qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
break;
}
trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
*data = ret;
return MEMTX_OK;
}
static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
MemTxAttrs attrs)
{
int i, mask = 0, data = 0;
/*
* bit 27-30 is mask for byte writing,
* if the mask is 0, we need not to do anything.
*/
if ((val >> 27) & 0xf) {
data = address_space_ldl(env->address_space_iocsr, addr,
attrs, NULL);
for (i = 0; i < 4; i++) {
/* get mask for byte writing */
if (val & (0x1 << (27 + i))) {
mask |= 0xff << (i * 8);
}
}
}
data &= mask;
data |= (val >> 32) & ~mask;
address_space_stl(env->address_space_iocsr, addr,
data, attrs, NULL);
}
static int archid_cmp(const void *a, const void *b)
{
CPUArchId *archid_a = (CPUArchId *)a;
CPUArchId *archid_b = (CPUArchId *)b;
return archid_a->arch_id - archid_b->arch_id;
}
static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
{
CPUArchId apic_id, *found_cpu;
apic_id.arch_id = id;
found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
archid_cmp);
return found_cpu;
}
static CPUState *ipi_getcpu(int arch_id)
{
MachineState *machine = MACHINE(qdev_get_machine());
CPUArchId *archid;
archid = find_cpu_by_archid(machine, arch_id);
if (archid) {
return CPU(archid->cpu);
}
return NULL;
}
static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
cs = ipi_getcpu(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
attrs.requester_id = cs->cpu_index;
send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
return MEMTX_OK;
}
static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
hwaddr addr;
CPUState *cs;
cpuid = extract32(val, 16, 10);
cs = ipi_getcpu(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
addr = val & 0xffff;
attrs.requester_id = cs->cpu_index;
send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
return MEMTX_OK;
}
static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
LoongArchIPI *ipi = opaque;
IPICore *s;
int index = 0;
uint32_t cpuid;
uint8_t vector;
CPUState *cs;
s = &ipi->cpu[attrs.requester_id];
addr &= 0xff;
trace_loongarch_ipi_write(size, (uint64_t)addr, val);
switch (addr) {
case CORE_STATUS_OFF:
qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
break;
case CORE_EN_OFF:
s->en = val;
break;
case CORE_SET_OFF:
s->status |= val;
if (s->status != 0 && (s->status & s->en) != 0) {
qemu_irq_raise(s->irq);
}
break;
case CORE_CLEAR_OFF:
s->status &= ~val;
if (s->status == 0 && s->en != 0) {
qemu_irq_lower(s->irq);
}
break;
case CORE_BUF_20 ... CORE_BUF_38 + 4:
index = (addr - CORE_BUF_20) >> 2;
s->buf[index] = val;
break;
case IOCSR_IPI_SEND:
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
cs = ipi_getcpu(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
attrs.requester_id = cs->cpu_index;
loongarch_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs);
break;
default:
qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
break;
}
return MEMTX_OK;
}
static const MemoryRegionOps loongarch_ipi_ops = {
.read_with_attrs = loongarch_ipi_readl,
.write_with_attrs = loongarch_ipi_writel,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 4,
.valid.max_access_size = 8,
.endianness = DEVICE_LITTLE_ENDIAN,
};
/* mail send and any send only support writeq */
static MemTxResult loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
MemTxResult ret = MEMTX_OK;
addr &= 0xfff;
switch (addr) {
case MAIL_SEND_OFFSET:
ret = mail_send(val, attrs);
break;
case ANY_SEND_OFFSET:
ret = any_send(val, attrs);
break;
default:
break;
}
return ret;
}
static const MemoryRegionOps loongarch_ipi64_ops = {
.write_with_attrs = loongarch_ipi_writeq,
.impl.min_access_size = 8,
.impl.max_access_size = 8,
.valid.min_access_size = 8,
.valid.max_access_size = 8,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
{
LoongArchIPI *s = LOONGARCH_IPI(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
if (s->num_cpu == 0) {
error_setg(errp, "num-cpu must be at least 1");
return;
}
memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongarch_ipi_ops,
s, "loongarch_ipi_iocsr", 0x48);
/* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
s->ipi_iocsr_mem.disable_reentrancy_guard = true;
sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
&loongarch_ipi64_ops,
s, "loongarch_ipi64_iocsr", 0x118);
sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
s->cpu = g_new0(IPICore, s->num_cpu);
if (s->cpu == NULL) {
error_setg(errp, "Memory allocation for ExtIOICore faile");
return;
}
for (i = 0; i < s->num_cpu; i++) {
qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
}
}
static const VMStateDescription vmstate_ipi_core = {
.name = "ipi-single",
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(status, IPICore),
VMSTATE_UINT32(en, IPICore),
VMSTATE_UINT32(set, IPICore),
VMSTATE_UINT32(clear, IPICore),
VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_loongarch_ipi = {
.name = TYPE_LOONGARCH_IPI,
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchIPI, num_cpu,
vmstate_ipi_core, IPICore),
VMSTATE_END_OF_LIST()
}
};
static Property ipi_properties[] = {
DEFINE_PROP_UINT32("num-cpu", LoongArchIPI, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = loongarch_ipi_realize;
device_class_set_props(dc, ipi_properties);
dc->vmsd = &vmstate_loongarch_ipi;
}
static void loongarch_ipi_finalize(Object *obj)
{
LoongArchIPI *s = LOONGARCH_IPI(obj);
g_free(s->cpu);
}
static const TypeInfo loongarch_ipi_info = {
.name = TYPE_LOONGARCH_IPI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LoongArchIPI),
.class_init = loongarch_ipi_class_init,
.instance_finalize = loongarch_ipi_finalize,
};
static void loongarch_ipi_register_types(void)
{
type_register_static(&loongarch_ipi_info);
}
type_init(loongarch_ipi_register_types)

125
hw/intc/loongson_ipi.c
View File

@ -23,16 +23,14 @@
#endif
#include "trace.h"
static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
IPICore *s;
LoongsonIPI *ipi = opaque;
IPICore *s = opaque;
uint64_t ret = 0;
int index = 0;
s = &ipi->cpu[attrs.requester_id];
addr &= 0xff;
switch (addr) {
case CORE_STATUS_OFF:
@ -61,6 +59,21 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr,
return MEMTX_OK;
}
static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr,
uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
LoongsonIPI *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
s = &ipi->cpu[attrs.requester_id];
return loongson_ipi_core_readl(s, addr, data, size, attrs);
}
static AddressSpace *get_cpu_iocsr_as(CPUState *cpu)
{
#ifdef TARGET_LOONGARCH64
@ -105,39 +118,6 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr,
return MEMTX_OK;
}
static int archid_cmp(const void *a, const void *b)
{
CPUArchId *archid_a = (CPUArchId *)a;
CPUArchId *archid_b = (CPUArchId *)b;
return archid_a->arch_id - archid_b->arch_id;
}
static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
{
CPUArchId apic_id, *found_cpu;
apic_id.arch_id = id;
found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
archid_cmp);
return found_cpu;
}
static CPUState *ipi_getcpu(int arch_id)
{
MachineState *machine = MACHINE(qdev_get_machine());
CPUArchId *archid;
archid = find_cpu_by_archid(machine, arch_id);
if (archid) {
return CPU(archid->cpu);
}
return NULL;
}
static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
{
uint32_t cpuid;
@ -145,7 +125,7 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
CPUState *cs;
cpuid = extract32(val, 16, 10);
cs = ipi_getcpu(cpuid);
cs = cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@ -163,7 +143,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
CPUState *cs;
cpuid = extract32(val, 16, 10);
cs = ipi_getcpu(cpuid);
cs = cpu_by_arch_id(cpuid);
if (cs == NULL) {
return MEMTX_DECODE_ERROR;
}
@ -174,17 +154,17 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
return send_ipi_data(cs, val, addr, attrs);
}
static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
LoongsonIPI *ipi = opaque;
IPICore *s;
IPICore *s = opaque;
LoongsonIPI *ipi = s->ipi;
int index = 0;
uint32_t cpuid;
uint8_t vector;
CPUState *cs;
s = &ipi->cpu[attrs.requester_id];
addr &= 0xff;
trace_loongson_ipi_write(size, (uint64_t)addr, val);
switch (addr) {
@ -214,14 +194,12 @@ static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
cpuid = extract32(val, 16, 10);
/* IPI status vector */
vector = extract8(val, 0, 5);
cs = ipi_getcpu(cpuid);
if (cs == NULL) {
cs = cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
/* override requester_id */
attrs.requester_id = cs->cpu_index;
loongson_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs);
loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF,
BIT(vector), 4, attrs);
break;
default:
qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
@ -231,9 +209,34 @@ static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
return MEMTX_OK;
}
static const MemoryRegionOps loongson_ipi_ops = {
.read_with_attrs = loongson_ipi_readl,
.write_with_attrs = loongson_ipi_writel,
static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
LoongsonIPI *ipi = opaque;
IPICore *s;
if (attrs.requester_id >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR;
}
s = &ipi->cpu[attrs.requester_id];
return loongson_ipi_core_writel(s, addr, val, size, attrs);
}
static const MemoryRegionOps loongson_ipi_core_ops = {
.read_with_attrs = loongson_ipi_core_readl,
.write_with_attrs = loongson_ipi_core_writel,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 4,
.valid.max_access_size = 8,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps loongson_ipi_iocsr_ops = {
.read_with_attrs = loongson_ipi_iocsr_readl,
.write_with_attrs = loongson_ipi_iocsr_writel,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 4,
@ -282,7 +285,8 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
return;
}
memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_ops,
memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev),
&loongson_ipi_iocsr_ops,
s, "loongson_ipi_iocsr", 0x48);
/* loongson_ipi_iocsr performs re-entrant IO through ipi_send */
@ -297,11 +301,18 @@ static void loongson_ipi_realize(DeviceState *dev, Error **errp)
s->cpu = g_new0(IPICore, s->num_cpu);
if (s->cpu == NULL) {
error_setg(errp, "Memory allocation for ExtIOICore faile");
error_setg(errp, "Memory allocation for IPICore faile");
return;
}
for (i = 0; i < s->num_cpu; i++) {
s->cpu[i].ipi = s;
s->cpu[i].ipi_mmio_mem = g_new0(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i);
memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev),
&loongson_ipi_core_ops, &s->cpu[i], name, 0x48);
sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem);
qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
}
}

5
hw/intc/m68k_irqc.c
View File

@ -10,7 +10,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/qdev-properties.h"
#include "hw/nmi.h"
#include "hw/intc/intc.h"
@ -27,10 +26,10 @@ static bool m68k_irqc_get_statistics(InterruptStatsProvider *obj,
return true;
}
static void m68k_irqc_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void m68k_irqc_print_info(InterruptStatsProvider *obj, GString *buf)
{
M68KIRQCState *s = M68K_IRQC(obj);
monitor_printf(mon, "m68k-irqc: ipr=0x%x\n", s->ipr);
g_string_append_printf(buf, "m68k-irqc: ipr=0x%x\n", s->ipr);
}
static void m68k_set_irq(void *opaque, int irq, int level)

38
hw/intc/pnv_xive.c
View File

@ -15,7 +15,6 @@
#include "sysemu/cpus.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"
#include "monitor/monitor.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_chip.h"
@ -1831,7 +1830,7 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
};
static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx,
Monitor *mon)
GString *buf)
{
uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1);
uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1);
@ -1840,12 +1839,12 @@ static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx,
return;
}
monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx,
eq_blk, eq_idx,
xive_get_field32(NVT_W4_IPB, nvt->w4));
g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x\n",
nvt_idx, eq_blk, eq_idx,
xive_get_field32(NVT_W4_IPB, nvt->w4));
}
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
void pnv_xive_pic_print_info(PnvXive *xive, GString *buf)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
uint8_t blk = pnv_xive_block_id(xive);
@ -1858,39 +1857,40 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
int i;
uint64_t xive_nvt_per_subpage;
monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
g_string_append_printf(buf, "XIVE[%x] #%d Source %08x .. %08x\n",
chip_id, blk, srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, buf);
monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
g_string_append_printf(buf, "XIVE[%x] #%d EAT %08x .. %08x\n",
chip_id, blk, srcno0, srcno0 + nr_ipis - 1);
for (i = 0; i < nr_ipis; i++) {
if (xive_router_get_eas(xrtr, blk, i, &eas)) {
break;
}
if (!xive_eas_is_masked(&eas)) {
xive_eas_pic_print_info(&eas, i, mon);
xive_eas_pic_print_info(&eas, i, buf);
}
}
monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
g_string_append_printf(buf, "XIVE[%x] #%d ENDT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_pic_print_info(&end, i++, mon);
xive_end_pic_print_info(&end, i++, buf);
}
monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
g_string_append_printf(buf, "XIVE[%x] #%d END Escalation EAT\n",
chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
xive_end_eas_pic_print_info(&end, i++, buf);
}
monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk,
0, XIVE_NVT_COUNT - 1);
g_string_append_printf(buf, "XIVE[%x] #%d NVTT %08x .. %08x\n",
chip_id, blk, 0, XIVE_NVT_COUNT - 1);
xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT);
for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) {
while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) {
xive_nvt_pic_print_info(&nvt, i++, mon);
xive_nvt_pic_print_info(&nvt, i++, buf);
}
}
}

48
hw/intc/pnv_xive2.c
View File

@ -13,7 +13,6 @@
#include "target/ppc/cpu.h"
#include "sysemu/cpus.h"
#include "sysemu/dma.h"
#include "monitor/monitor.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_chip.h"
@ -2027,7 +2026,7 @@ static void pnv_xive2_register_types(void)
type_init(pnv_xive2_register_types)
static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,
Monitor *mon)
GString *buf)
{
uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
@ -2036,21 +2035,21 @@ static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,
return;
}
monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x",
nvp_idx, eq_blk, eq_idx,
xive_get_field32(NVP2_W2_IPB, nvp->w2));
g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x",
nvp_idx, eq_blk, eq_idx,
xive_get_field32(NVP2_W2_IPB, nvp->w2));
/*
* When the NVP is HW controlled, more fields are updated
*/
if (xive2_nvp_is_hw(nvp)) {
monitor_printf(mon, " CPPR:%02x",
xive_get_field32(NVP2_W2_CPPR, nvp->w2));
g_string_append_printf(buf, " CPPR:%02x",
xive_get_field32(NVP2_W2_CPPR, nvp->w2));
if (xive2_nvp_is_co(nvp)) {
monitor_printf(mon, " CO:%04x",
xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
g_string_append_printf(buf, " CO:%04x",
xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
}
}
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
/*
@ -2104,7 +2103,7 @@ static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type)
return (1ull << page_shift) / info->size;
}
void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon)
void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf)
{
Xive2Router *xrtr = XIVE2_ROUTER(xive);
uint8_t blk = pnv_xive2_block_id(xive);
@ -2117,39 +2116,40 @@ void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon)
int i;
uint64_t xive_nvp_per_subpage;
monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
srcno0 + nr_esbs - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
g_string_append_printf(buf, "XIVE[%x] Source %08x .. %08x\n",
blk, srcno0, srcno0 + nr_esbs - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, buf);
monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
srcno0 + nr_esbs - 1);
g_string_append_printf(buf, "XIVE[%x] EAT %08x .. %08x\n",
blk, srcno0, srcno0 + nr_esbs - 1);
for (i = 0; i < nr_esbs; i++) {
if (xive2_router_get_eas(xrtr, blk, i, &eas)) {
break;
}
if (!xive2_eas_is_masked(&eas)) {
xive2_eas_pic_print_info(&eas, i, mon);
xive2_eas_pic_print_info(&eas, i, buf);
}
}
monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
g_string_append_printf(buf, "XIVE[%x] #%d END Escalation EAT\n",
chip_id, blk);
i = 0;
while (!xive2_router_get_end(xrtr, blk, i, &end)) {
xive2_end_eas_pic_print_info(&end, i++, mon);
xive2_end_eas_pic_print_info(&end, i++, buf);
}
monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
g_string_append_printf(buf, "XIVE[%x] #%d ENDT\n", chip_id, blk);
i = 0;
while (!xive2_router_get_end(xrtr, blk, i, &end)) {
xive2_end_pic_print_info(&end, i++, mon);
xive2_end_pic_print_info(&end, i++, buf);
}
monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk,
0, XIVE2_NVP_COUNT - 1);
g_string_append_printf(buf, "XIVE[%x] #%d NVPT %08x .. %08x\n",
chip_id, blk, 0, XIVE2_NVP_COUNT - 1);
xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP);
for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) {
while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) {
xive2_nvp_pic_print_info(&nvp, i++, mon);
xive2_nvp_pic_print_info(&nvp, i++, buf);
}
}
}

11
hw/intc/slavio_intctl.c
View File

@ -24,7 +24,6 @@
#include "qemu/osdep.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "hw/intc/intc.h"
@ -401,17 +400,17 @@ static bool slavio_intctl_get_statistics(InterruptStatsProvider *obj,
}
#endif
static void slavio_intctl_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void slavio_intctl_print_info(InterruptStatsProvider *obj, GString *buf)
{
SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
int i;
for (i = 0; i < MAX_CPUS; i++) {
monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
s->slaves[i].intreg_pending);
g_string_append_printf(buf, "per-cpu %d: pending 0x%08x\n", i,
s->slaves[i].intreg_pending);
}
monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
s->intregm_pending, s->intregm_disabled);
g_string_append_printf(buf, "master: pending 0x%08x, disabled 0x%08x\n",
s->intregm_pending, s->intregm_disabled);
}
static void slavio_intctl_init(Object *obj)

41
hw/intc/spapr_xive.c
View File

@ -16,7 +16,6 @@
#include "sysemu/cpus.h"
#include "sysemu/reset.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
@ -132,7 +131,7 @@ static int spapr_xive_target_to_end(uint32_t target, uint8_t prio,
* structure dumping only the information related to the OS EQ.
*/
static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end,
Monitor *mon)
GString *buf)
{
uint64_t qaddr_base = xive_end_qaddr(end);
uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
@ -142,11 +141,11 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end,
uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6);
uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7);
monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d",
spapr_xive_nvt_to_target(0, nvt),
priority, qindex, qentries, qaddr_base, qgen);
g_string_append_printf(buf, "%3d/%d % 6d/%5d @%"PRIx64" ^%d",
spapr_xive_nvt_to_target(0, nvt),
priority, qindex, qentries, qaddr_base, qgen);
xive_end_queue_pic_print_info(end, 6, mon);
xive_end_queue_pic_print_info(end, 6, buf);
}
/*
@ -156,7 +155,7 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end,
#define spapr_xive_in_kernel(xive) \
(kvm_irqchip_in_kernel() && (xive)->fd != -1)
static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
static void spapr_xive_pic_print_info(SpaprXive *xive, GString *buf)
{
XiveSource *xsrc = &xive->source;
int i;
@ -171,7 +170,7 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
}
}
monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n");
g_string_append_printf(buf, " LISN PQ EISN CPU/PRIO EQ\n");
for (i = 0; i < xive->nr_irqs; i++) {
uint8_t pq = xive_source_esb_get(xsrc, i);
@ -181,13 +180,13 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
continue;
}
monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i,
xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_source_is_asserted(xsrc, i) ? 'A' : ' ',
xive_eas_is_masked(eas) ? "M" : " ",
(int) xive_get_field64(EAS_END_DATA, eas->w));
g_string_append_printf(buf, " %08x %s %c%c%c %s %08x ", i,
xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_source_is_asserted(xsrc, i) ? 'A' : ' ',
xive_eas_is_masked(eas) ? "M" : " ",
(int) xive_get_field64(EAS_END_DATA, eas->w));
if (!xive_eas_is_masked(eas)) {
uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w);
@ -197,10 +196,11 @@ static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
end = &xive->endt[end_idx];
if (xive_end_is_valid(end)) {
spapr_xive_end_pic_print_info(xive, end, mon);
spapr_xive_end_pic_print_info(xive, end, buf);
}
}
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
}
@ -699,7 +699,7 @@ static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val)
}
}
static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon)
static void spapr_xive_print_info(SpaprInterruptController *intc, GString *buf)
{
SpaprXive *xive = SPAPR_XIVE(intc);
CPUState *cs;
@ -707,10 +707,9 @@ static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon)
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, buf);
}
spapr_xive_pic_print_info(xive, mon);
spapr_xive_pic_print_info(xive, buf);
}
static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers,

25
hw/intc/xics.c
View File

@ -35,14 +35,13 @@
#include "qemu/module.h"
#include "qapi/visitor.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
#include "target/ppc/cpu.h"
void icp_pic_print_info(ICPState *icp, Monitor *mon)
void icp_pic_print_info(ICPState *icp, GString *buf)
{
int cpu_index;
@ -63,17 +62,17 @@ void icp_pic_print_info(ICPState *icp, Monitor *mon)
icp_synchronize_state(icp);
}
monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
cpu_index, icp->xirr, icp->xirr_owner,
icp->pending_priority, icp->mfrr);
g_string_append_printf(buf, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
cpu_index, icp->xirr, icp->xirr_owner,
icp->pending_priority, icp->mfrr);
}
void ics_pic_print_info(ICSState *ics, Monitor *mon)
void ics_pic_print_info(ICSState *ics, GString *buf)
{
uint32_t i;
monitor_printf(mon, "ICS %4x..%4x %p\n",
ics->offset, ics->offset + ics->nr_irqs - 1, ics);
g_string_append_printf(buf, "ICS %4x..%4x %p\n",
ics->offset, ics->offset + ics->nr_irqs - 1, ics);
if (!ics->irqs) {
return;
@ -89,11 +88,11 @@ void ics_pic_print_info(ICSState *ics, Monitor *mon)
if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
continue;
}
monitor_printf(mon, " %4x %s %02x %02x\n",
ics->offset + i,
(irq->flags & XICS_FLAGS_IRQ_LSI) ?
"LSI" : "MSI",
irq->priority, irq->status);
g_string_append_printf(buf, " %4x %s %02x %02x\n",
ics->offset + i,
(irq->flags & XICS_FLAGS_IRQ_LSI) ?
"LSI" : "MSI",
irq->priority, irq->status);
}
}

7
hw/intc/xics_spapr.c
View File

@ -395,7 +395,7 @@ static void xics_spapr_set_irq(SpaprInterruptController *intc, int irq, int val)
ics_set_irq(ics, srcno, val);
}
static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
static void xics_spapr_print_info(SpaprInterruptController *intc, GString *buf)
{
ICSState *ics = ICS_SPAPR(intc);
CPUState *cs;
@ -403,10 +403,9 @@ static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
icp_pic_print_info(spapr_cpu_state(cpu)->icp, buf);
}
ics_pic_print_info(ics, mon);
ics_pic_print_info(ics, buf);
}
static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)

108
hw/intc/xive.c
View File

@ -17,7 +17,6 @@
#include "sysemu/reset.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/irq.h"
#include "hw/ppc/xive.h"
#include "hw/ppc/xive2.h"
@ -669,7 +668,7 @@ static const char * const xive_tctx_ring_names[] = {
xpc->in_kernel ? xpc->in_kernel(xptr) : false; \
}))
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon)
void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf)
{
int cpu_index;
int i;
@ -693,13 +692,14 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon)
}
}
monitor_printf(mon, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
" W2\n", cpu_index);
g_string_append_printf(buf, "CPU[%04x]: "
"QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2\n",
cpu_index);
for (i = 0; i < XIVE_TM_RING_COUNT; i++) {
char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]);
monitor_printf(mon, "CPU[%04x]: %4s %s\n", cpu_index,
xive_tctx_ring_names[i], s);
g_string_append_printf(buf, "CPU[%04x]: %4s %s\n",
cpu_index, xive_tctx_ring_names[i], s);
g_free(s);
}
}
@ -1207,22 +1207,20 @@ void xive_source_set_irq(void *opaque, int srcno, int val)
}
}
void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon)
void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, GString *buf)
{
int i;
for (i = 0; i < xsrc->nr_irqs; i++) {
for (unsigned i = 0; i < xsrc->nr_irqs; i++) {
uint8_t pq = xive_source_esb_get(xsrc, i);
if (pq == XIVE_ESB_OFF) {
continue;
}
monitor_printf(mon, " %08x %s %c%c%c\n", i + offset,
xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_source_is_asserted(xsrc, i) ? 'A' : ' ');
g_string_append_printf(buf, " %08x %s %c%c%c\n", i + offset,
xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI",
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_source_is_asserted(xsrc, i) ? 'A' : ' ');
}
}
@ -1322,7 +1320,7 @@ static const TypeInfo xive_source_info = {
* XiveEND helpers
*/
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon)
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf)
{
uint64_t qaddr_base = xive_end_qaddr(end);
uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
@ -1333,7 +1331,7 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon)
/*
* print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
*/
monitor_printf(mon, " [ ");
g_string_append_printf(buf, " [ ");
qindex = (qindex - (width - 1)) & (qentries - 1);
for (i = 0; i < width; i++) {
uint64_t qaddr = qaddr_base + (qindex << 2);
@ -1345,14 +1343,14 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon)
HWADDR_PRIx "\n", qaddr);
return;
}
monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "",
be32_to_cpu(qdata));
g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "",
be32_to_cpu(qdata));
qindex = (qindex + 1) & (qentries - 1);
}
monitor_printf(mon, "]");
g_string_append_c(buf, ']');
}
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf)
{
uint64_t qaddr_base = xive_end_qaddr(end);
uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
@ -1371,26 +1369,27 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
pq = xive_get_field32(END_W1_ESn, end->w1);
monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_end_is_valid(end) ? 'v' : '-',
xive_end_is_enqueue(end) ? 'q' : '-',
xive_end_is_notify(end) ? 'n' : '-',
xive_end_is_backlog(end) ? 'b' : '-',
xive_end_is_escalate(end) ? 'e' : '-',
xive_end_is_uncond_escalation(end) ? 'u' : '-',
xive_end_is_silent_escalation(end) ? 's' : '-',
xive_end_is_firmware(end) ? 'f' : '-',
priority, nvt_blk, nvt_idx);
g_string_append_printf(buf,
" %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_end_is_valid(end) ? 'v' : '-',
xive_end_is_enqueue(end) ? 'q' : '-',
xive_end_is_notify(end) ? 'n' : '-',
xive_end_is_backlog(end) ? 'b' : '-',
xive_end_is_escalate(end) ? 'e' : '-',
xive_end_is_uncond_escalation(end) ? 'u' : '-',
xive_end_is_silent_escalation(end) ? 's' : '-',
xive_end_is_firmware(end) ? 'f' : '-',
priority, nvt_blk, nvt_idx);
if (qaddr_base) {
monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d",
qaddr_base, qindex, qentries, qgen);
xive_end_queue_pic_print_info(end, 6, mon);
g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
qaddr_base, qindex, qentries, qgen);
xive_end_queue_pic_print_info(end, 6, buf);
}
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
static void xive_end_enqueue(XiveEND *end, uint32_t data)
@ -1419,8 +1418,7 @@ static void xive_end_enqueue(XiveEND *end, uint32_t data)
end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex);
}
void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx,
Monitor *mon)
void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf)
{
XiveEAS *eas = (XiveEAS *) &end->w4;
uint8_t pq;
@ -1431,15 +1429,15 @@ void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx,
pq = xive_get_field32(END_W1_ESe, end->w1);
monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_eas_is_valid(eas) ? 'V' : ' ',
xive_eas_is_masked(eas) ? 'M' : ' ',
(uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive_eas_is_valid(eas) ? 'V' : ' ',
xive_eas_is_masked(eas) ? 'M' : ' ',
(uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
}
/*
@ -1917,17 +1915,17 @@ static const TypeInfo xive_router_info = {
}
};
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon)
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf)
{
if (!xive_eas_is_valid(eas)) {
return;
}
monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n",
lisn, xive_eas_is_masked(eas) ? "M" : " ",
(uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n",
lisn, xive_eas_is_masked(eas) ? "M" : " ",
(uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
}
/*

87
hw/intc/xive2.c
View File

@ -15,7 +15,6 @@
#include "sysemu/cpus.h"
#include "sysemu/dma.h"
#include "hw/qdev-properties.h"
#include "monitor/monitor.h"
#include "hw/ppc/xive.h"
#include "hw/ppc/xive2.h"
#include "hw/ppc/xive2_regs.h"
@ -27,21 +26,20 @@ uint32_t xive2_router_get_config(Xive2Router *xrtr)
return xrc->get_config(xrtr);
}
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon)
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
{
if (!xive2_eas_is_valid(eas)) {
return;
}
monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n",
lisn, xive2_eas_is_masked(eas) ? "M" : " ",
(uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n",
lisn, xive2_eas_is_masked(eas) ? "M" : " ",
(uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
}
void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
Monitor *mon)
void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf)
{
uint64_t qaddr_base = xive2_end_qaddr(end);
uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
@ -52,7 +50,7 @@ void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
/*
* print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
*/
monitor_printf(mon, " [ ");
g_string_append_printf(buf, " [ ");
qindex = (qindex - (width - 1)) & (qentries - 1);
for (i = 0; i < width; i++) {
uint64_t qaddr = qaddr_base + (qindex << 2);
@ -64,14 +62,14 @@ void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
HWADDR_PRIx "\n", qaddr);
return;
}
monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "",
be32_to_cpu(qdata));
g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "",
be32_to_cpu(qdata));
qindex = (qindex + 1) & (qentries - 1);
}
monitor_printf(mon, "]");
g_string_append_printf(buf, "]");
}
void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon)
void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf)
{
uint64_t qaddr_base = xive2_end_qaddr(end);
uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
@ -90,33 +88,34 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon)
pq = xive_get_field32(END2_W1_ESn, end->w1);
monitor_printf(mon,
" %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive2_end_is_valid(end) ? 'v' : '-',
xive2_end_is_enqueue(end) ? 'q' : '-',
xive2_end_is_notify(end) ? 'n' : '-',
xive2_end_is_backlog(end) ? 'b' : '-',
xive2_end_is_escalate(end) ? 'e' : '-',
xive2_end_is_escalate_end(end) ? 'N' : '-',
xive2_end_is_uncond_escalation(end) ? 'u' : '-',
xive2_end_is_silent_escalation(end) ? 's' : '-',
xive2_end_is_firmware1(end) ? 'f' : '-',
xive2_end_is_firmware2(end) ? 'F' : '-',
priority, nvp_blk, nvp_idx);
g_string_append_printf(buf,
" %08x %c%c %c%c%c%c%c%c%c%c%c%c "
"prio:%d nvp:%02x/%04x",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive2_end_is_valid(end) ? 'v' : '-',
xive2_end_is_enqueue(end) ? 'q' : '-',
xive2_end_is_notify(end) ? 'n' : '-',
xive2_end_is_backlog(end) ? 'b' : '-',
xive2_end_is_escalate(end) ? 'e' : '-',
xive2_end_is_escalate_end(end) ? 'N' : '-',
xive2_end_is_uncond_escalation(end) ? 'u' : '-',
xive2_end_is_silent_escalation(end) ? 's' : '-',
xive2_end_is_firmware1(end) ? 'f' : '-',
xive2_end_is_firmware2(end) ? 'F' : '-',
priority, nvp_blk, nvp_idx);
if (qaddr_base) {
monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d",
qaddr_base, qindex, qentries, qgen);
xive2_end_queue_pic_print_info(end, 6, mon);
g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
qaddr_base, qindex, qentries, qgen);
xive2_end_queue_pic_print_info(end, 6, buf);
}
monitor_printf(mon, "\n");
g_string_append_c(buf, '\n');
}
void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
Monitor *mon)
GString *buf)
{
Xive2Eas *eas = (Xive2Eas *) &end->w4;
uint8_t pq;
@ -127,15 +126,15 @@ void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
pq = xive_get_field32(END2_W1_ESe, end->w1);
monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive2_eas_is_valid(eas) ? 'v' : ' ',
xive2_eas_is_masked(eas) ? 'M' : ' ',
(uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
end_idx,
pq & XIVE_ESB_VAL_P ? 'P' : '-',
pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
xive2_eas_is_valid(eas) ? 'v' : ' ',
xive2_eas_is_masked(eas) ? 'M' : ' ',
(uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
(uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
(uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
}
static void xive2_end_enqueue(Xive2End *end, uint32_t data)

4
hw/loongarch/virt.c
View File

@ -556,7 +556,7 @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
return;
}
smbios_set_defaults("QEMU", product, mc->name, true);
smbios_set_defaults("QEMU", product, mc->name);
smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64,
NULL, 0,
@ -1245,7 +1245,7 @@ static bool memhp_type_supported(DeviceState *dev)
static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
}
static void virt_device_pre_plug(HotplugHandler *hotplug_dev,

12
hw/mem/memory-device.c
View File

@ -345,7 +345,7 @@ uint64_t get_plugged_memory_size(void)
}
void memory_device_pre_plug(MemoryDeviceState *md, MachineState *ms,
const uint64_t *legacy_align, Error **errp)
Error **errp)
{
const MemoryDeviceClass *mdc = MEMORY_DEVICE_GET_CLASS(md);
Error *local_err = NULL;
@ -388,14 +388,10 @@ void memory_device_pre_plug(MemoryDeviceState *md, MachineState *ms,
return;
}
if (legacy_align) {
align = *legacy_align;
} else {
if (mdc->get_min_alignment) {
align = mdc->get_min_alignment(md);
}
align = MAX(align, memory_region_get_alignment(mr));
if (mdc->get_min_alignment) {
align = mdc->get_min_alignment(md);
}
align = MAX(align, memory_region_get_alignment(mr));
addr = mdc->get_addr(md);
addr = memory_device_get_free_addr(ms, !addr ? NULL : &addr, align,
memory_region_size(mr), &local_err);

6
hw/mem/pc-dimm.c
View File

@ -44,8 +44,7 @@ static MemoryRegion *pc_dimm_get_memory_region(PCDIMMDevice *dimm, Error **errp)
return host_memory_backend_get_memory(dimm->hostmem);
}
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,
const uint64_t *legacy_align, Error **errp)
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine, Error **errp)
{
Error *local_err = NULL;
int slot;
@ -70,8 +69,7 @@ void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,
&error_abort);
trace_mhp_pc_dimm_assigned_slot(slot);
memory_device_pre_plug(MEMORY_DEVICE(dimm), machine, legacy_align,
errp);
memory_device_pre_plug(MEMORY_DEVICE(dimm), machine, errp);
}
void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine)

1
hw/mips/Kconfig
View File

@ -67,6 +67,7 @@ config LOONGSON3V
imply USB_OHCI_PCI
select SERIAL
select GOLDFISH_RTC
select LOONGSON_IPI
select LOONGSON_LIOINTC
select PCI_EXPRESS_GENERIC_BRIDGE
select MSI_NONBROKEN

2
hw/mips/loongson3_bootp.c
View File

@ -25,8 +25,6 @@
#include "hw/boards.h"
#include "hw/mips/loongson3_bootp.h"
#define LOONGSON3_CORE_PER_NODE 4
static void init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
{
struct efi_cpuinfo_loongson *c = g_cpuinfo;

3
hw/mips/loongson3_bootp.h
View File

@ -200,6 +200,8 @@ struct boot_params {
struct efi_reset_system_t reset_system;
};
#define LOONGSON3_CORE_PER_NODE 4
/* Overall MMIO & Memory layout */
enum {
VIRT_LOWMEM,
@ -211,6 +213,7 @@ enum {
VIRT_BIOS_ROM,
VIRT_UART,
VIRT_LIOINTC,
VIRT_IPI,
VIRT_PCIE_MMIO,
VIRT_HIGHMEM
};

39
hw/mips/loongson3_virt.c
View File

@ -36,6 +36,7 @@
#include "hw/mips/loongson3_bootp.h"
#include "hw/misc/unimp.h"
#include "hw/intc/i8259.h"
#include "hw/intc/loongson_ipi.h"
#include "hw/loader.h"
#include "hw/isa/superio.h"
#include "hw/pci/msi.h"
@ -74,6 +75,7 @@ const MemMapEntry virt_memmap[] = {
[VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
[VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
[VIRT_UART] = { 0x1fe001e0, 0x8 },
[VIRT_IPI] = { 0x3ff01000, 0x400 },
[VIRT_LIOINTC] = { 0x3ff01400, 0x64 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_HIGHMEM] = { 0x80000000, 0x0 }, /* Variable */
@ -485,6 +487,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
Clock *cpuclk;
CPUMIPSState *env;
DeviceState *liointc;
DeviceState *ipi = NULL;
char *filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *kernel_filename = machine->kernel_filename;
@ -494,6 +497,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *iomem = g_new(MemoryRegion, 1);
MemoryRegion *iocsr = g_new(MemoryRegion, 1);
/* TODO: TCG will support all CPU types */
if (!kvm_enabled()) {
@ -527,6 +531,19 @@ static void mips_loongson3_virt_init(MachineState *machine)
create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX);
/* IPI controller is in kernel for KVM */
if (!kvm_enabled()) {
ipi = qdev_new(TYPE_LOONGSON_IPI);
qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX,
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
memory_region_add_subregion(iocsr, MAIL_SEND_ADDR,
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
}
liointc = qdev_new("loongson.liointc");
sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
@ -543,6 +560,8 @@ static void mips_loongson3_virt_init(MachineState *machine)
clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ);
for (i = 0; i < machine->smp.cpus; i++) {
int node = i / LOONGSON3_CORE_PER_NODE;
int core = i % LOONGSON3_CORE_PER_NODE;
int ip;
/* init CPUs */
@ -553,12 +572,28 @@ static void mips_loongson3_virt_init(MachineState *machine)
cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
if (i >= 4) {
if (ipi) {
hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
base += core * 0x100;
qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
}
if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
MemoryRegion *core_iocsr = g_new(MemoryRegion, 1);
g_autofree char *name = g_strdup_printf("core%d_iocsr", i);
memory_region_init_alias(core_iocsr, OBJECT(cpu), name,
iocsr, 0, UINT32_MAX);
memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr,
0, core_iocsr);
}
if (node > 0) {
continue; /* Only node-0 can be connected to LIOINTC */
}
for (ip = 0; ip < 4 ; ip++) {
int pin = i * 4 + ip;
int pin = core * LOONGSON3_CORE_PER_NODE + ip;
sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
pin, cpu->env.irq[ip + 2]);
}

21
hw/pci-host/pnv_phb3_msi.c
View File

@ -13,7 +13,6 @@
#include "hw/pci-host/pnv_phb3.h"
#include "hw/ppc/pnv.h"
#include "hw/pci/msi.h"
#include "monitor/monitor.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "sysemu/reset.h"
@ -316,13 +315,13 @@ static void pnv_phb3_msi_register_types(void)
type_init(pnv_phb3_msi_register_types);
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, Monitor *mon)
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, GString *buf)
{
ICSState *ics = ICS(msi);
int i;
monitor_printf(mon, "ICS %4x..%4x %p\n",
ics->offset, ics->offset + ics->nr_irqs - 1, ics);
g_string_append_printf(buf, "ICS %4x..%4x %p\n",
ics->offset, ics->offset + ics->nr_irqs - 1, ics);
for (i = 0; i < ics->nr_irqs; i++) {
uint64_t ive;
@ -335,12 +334,12 @@ void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, Monitor *mon)
continue;
}
monitor_printf(mon, " %4x %c%c server=%04x prio=%02x gen=%d\n",
ics->offset + i,
GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-',
GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-',
(uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2,
(uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive),
(uint32_t) GETFIELD(IODA2_IVT_GEN, ive));
g_string_append_printf(buf, " %4x %c%c server=%04x prio=%02x gen=%d\n",
ics->offset + i,
GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-',
GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-',
(uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2,
(uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive),
(uint32_t) GETFIELD(IODA2_IVT_GEN, ive));
}
}

17
hw/pci-host/pnv_phb4.c
View File

@ -10,7 +10,6 @@
#include "qemu/log.h"
#include "qapi/visitor.h"
#include "qapi/error.h"
#include "monitor/monitor.h"
#include "target/ppc/cpu.h"
#include "hw/pci-host/pnv_phb4_regs.h"
#include "hw/pci-host/pnv_phb4.h"
@ -1801,17 +1800,19 @@ static void pnv_phb4_register_types(void)
type_init(pnv_phb4_register_types);
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)
void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf)
{
uint64_t notif_port =
phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K;
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE);
monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x %s @%"HWADDR_PRIx"\n",
phb->chip_id, phb->phb_id,
offset, offset + phb->xsrc.nr_irqs - 1,
abt ? "ABT" : "",
notif_port);
xive_source_pic_print_info(&phb->xsrc, 0, mon);
g_string_append_printf(buf,
"PHB4[%x:%x] Source %08x .. %08x "
"%s @%"HWADDR_PRIx"\n",
phb->chip_id, phb->phb_id,
offset, offset + phb->xsrc.nr_irqs - 1,
abt ? "ABT" : "",
notif_port);
xive_source_pic_print_info(&phb->xsrc, 0, buf);
}

96
hw/ppc/pnv.c
View File

@ -38,7 +38,6 @@
#include "hw/loader.h"
#include "hw/nmi.h"
#include "qapi/visitor.h"
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
#include "hw/ipmi/ipmi.h"
#include "target/ppc/mmu-hash64.h"
@ -764,45 +763,44 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
}
static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
int i;
ics_pic_print_info(&chip8->psi.ics, mon);
ics_pic_print_info(&chip8->psi.ics, buf);
for (i = 0; i < chip8->num_phbs; i++) {
PnvPHB *phb = chip8->phbs[i];
PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
ics_pic_print_info(&phb3->lsis, mon);
pnv_phb3_msi_pic_print_info(&phb3->msis, buf);
ics_pic_print_info(&phb3->lsis, buf);
}
}
static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
{
Monitor *mon = opaque;
GString *buf = opaque;
PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
if (!phb) {
return 0;
}
pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf);
return 0;
}
static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
pnv_xive_pic_print_info(&chip9->xive, mon);
pnv_psi_pic_print_info(&chip9->psi, mon);
pnv_xive_pic_print_info(&chip9->xive, buf);
pnv_psi_pic_print_info(&chip9->psi, buf);
object_child_foreach_recursive(OBJECT(chip),
pnv_chip_power9_pic_print_info_child, mon);
pnv_chip_power9_pic_print_info_child, buf);
}
static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
@ -842,15 +840,14 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
isa_realize_and_unref(dev, bus, &error_fatal);
}
static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
pnv_xive2_pic_print_info(&chip10->xive, mon);
pnv_psi_pic_print_info(&chip10->psi, mon);
pnv_xive2_pic_print_info(&chip10->xive, buf);
pnv_psi_pic_print_info(&chip10->psi, buf);
object_child_foreach_recursive(OBJECT(chip),
pnv_chip_power9_pic_print_info_child, mon);
pnv_chip_power9_pic_print_info_child, buf);
}
/* Always give the first 1GB to chip 0 else we won't boot */
@ -1122,9 +1119,9 @@ static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
}
static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
Monitor *mon)
GString *buf)
{
icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf);
}
/*
@ -1209,9 +1206,9 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
}
static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
Monitor *mon)
GString *buf)
{
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
}
static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@ -1253,9 +1250,9 @@ static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
}
static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
Monitor *mon)
GString *buf)
{
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
}
/*
@ -2264,6 +2261,21 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
return NULL;
}
static void pnv_chip_foreach_cpu(PnvChip *chip,
void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque),
void *opaque)
{
int i, j;
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pc = chip->cores[i];
for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) {
fn(chip, pc->threads[j], opaque);
}
}
}
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
@ -2332,23 +2344,25 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
}
static void pnv_pic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
void *opaque)
{
PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque);
}
static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
int i;
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
/* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
mon);
}
for (i = 0; i < pnv->num_chips; i++) {
PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
PnvChip *chip = pnv->chips[i];
/* First CPU presenters */
pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf);
/* Then other devices, PHB, PSI, XIVE */
PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf);
}
}
@ -2549,12 +2563,18 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
}
}
static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
{
async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
}
static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
{
CPUState *cs;
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
CPU_FOREACH(cs) {
async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
for (i = 0; i < pnv->num_chips; i++) {
pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL);
}
}

9
hw/ppc/pnv_psi.c
View File

@ -25,7 +25,6 @@
#include "qemu/module.h"
#include "sysemu/reset.h"
#include "qapi/error.h"
#include "monitor/monitor.h"
#include "hw/ppc/fdt.h"
@ -977,14 +976,14 @@ static void pnv_psi_register_types(void)
type_init(pnv_psi_register_types);
void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
void pnv_psi_pic_print_info(Pnv9Psi *psi9, GString *buf)
{
PnvPsi *psi = PNV_PSI(psi9);
uint32_t offset =
(psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
offset, offset + psi9->source.nr_irqs - 1);
xive_source_pic_print_info(&psi9->source, offset, mon);
g_string_append_printf(buf, "PSIHB Source %08x .. %08x\n",
offset, offset + psi9->source.nr_irqs - 1);
xive_source_pic_print_info(&psi9->source, offset, buf);
}

13
hw/ppc/spapr.c
View File

@ -89,8 +89,6 @@
#include "hw/ppc/spapr_nvdimm.h"
#include "hw/ppc/spapr_numa.h"
#include "monitor/monitor.h"
#include <libfdt.h>
/* SLOF memory layout:
@ -3700,7 +3698,7 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
return;
}
pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), errp);
}
struct SpaprDimmState {
@ -4526,14 +4524,13 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
return cpu ? spapr_cpu_state(cpu)->icp : NULL;
}
static void spapr_pic_print_info(InterruptStatsProvider *obj,
Monitor *mon)
static void spapr_pic_print_info(InterruptStatsProvider *obj, GString *buf)
{
SpaprMachineState *spapr = SPAPR_MACHINE(obj);
spapr_irq_print_info(spapr, mon);
monitor_printf(mon, "irqchip: %s\n",
kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
spapr_irq_print_info(spapr, buf);
g_string_append_printf(buf, "irqchip: %s\n",
kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
}
/*

4
hw/ppc/spapr_irq.c
View File

@ -265,12 +265,12 @@ static void spapr_set_irq(void *opaque, int irq, int level)
sicc->set_irq(spapr->active_intc, irq, level);
}
void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon)
void spapr_irq_print_info(SpaprMachineState *spapr, GString *buf)
{
SpaprInterruptControllerClass *sicc
= SPAPR_INTC_GET_CLASS(spapr->active_intc);
sicc->print_info(spapr->active_intc, mon);
sicc->print_info(spapr->active_intc, buf);
}
void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,

2
hw/riscv/virt.c
View File

@ -1277,7 +1277,7 @@ static void virt_build_smbios(RISCVVirtState *s)
product = "KVM Virtual Machine";
}
smbios_set_defaults("QEMU", product, mc->name, true);
smbios_set_defaults("QEMU", product, mc->name);
if (riscv_is_32bit(&s->soc[0])) {
smbios_set_default_processor_family(0x200);

27
hw/s390x/s390-skeys.c
View File

@ -23,6 +23,7 @@
#include "sysemu/kvm.h"
#include "migration/qemu-file-types.h"
#include "migration/register.h"
#include "trace.h"
#define S390_SKEYS_BUFFER_SIZE (128 * KiB) /* Room for 128k storage keys */
#define S390_SKEYS_SAVE_FLAG_EOS 0x01
@ -54,6 +55,32 @@ void s390_skeys_init(void)
qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
int s390_skeys_get(S390SKeysState *ks, uint64_t start_gfn,
uint64_t count, uint8_t *keys)
{
S390SKeysClass *kc = S390_SKEYS_GET_CLASS(ks);
int rc;
rc = kc->get_skeys(ks, start_gfn, count, keys);
if (rc) {
trace_s390_skeys_get_nonzero(rc);
}
return rc;
}
int s390_skeys_set(S390SKeysState *ks, uint64_t start_gfn,
uint64_t count, uint8_t *keys)
{
S390SKeysClass *kc = S390_SKEYS_GET_CLASS(ks);
int rc;
rc = kc->set_skeys(ks, start_gfn, count, keys);
if (rc) {
trace_s390_skeys_set_nonzero(rc);
}
return rc;
}
static void write_keys(FILE *f, uint8_t *keys, uint64_t startgfn,
uint64_t count, Error **errp)
{

4
hw/s390x/trace-events
View File

@ -36,3 +36,7 @@ s390_pci_unknown(const char *msg, uint32_t cmd) "%s unknown command 0x%x"
s390_pci_bar(uint32_t bar, uint32_t addr, uint64_t size, uint32_t barsize) "bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x"
s390_pci_nodev(const char *cmd, uint32_t fh) "%s no pci dev fh 0x%x"
s390_pci_invalid(const char *cmd, uint32_t fh) "%s invalid space fh 0x%x"
# s390-skeys.c
s390_skeys_get_nonzero(int rc) "SKEY: Call to get_skeys unexpectedly returned %d"
s390_skeys_set_nonzero(int rc) "SKEY: Call to set_skeys unexpectedly returned %d"

13
hw/smbios/smbios.c
View File

@ -30,7 +30,6 @@
#include "hw/pci/pci_device.h"
#include "smbios_build.h"
static bool smbios_uuid_encoded = true;
/*
* SMBIOS tables provided by user with '-smbios file=<foo>' option
*/
@ -600,11 +599,9 @@ static void smbios_build_type_0_table(void)
static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in)
{
memcpy(uuid, in, 16);
if (smbios_uuid_encoded) {
uuid->time_low = bswap32(uuid->time_low);
uuid->time_mid = bswap16(uuid->time_mid);
uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version);
}
uuid->time_low = bswap32(uuid->time_low);
uuid->time_mid = bswap16(uuid->time_mid);
uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version);
}
static void smbios_build_type_1_table(void)
@ -1017,11 +1014,9 @@ void smbios_set_default_processor_family(uint16_t processor_family)
}
void smbios_set_defaults(const char *manufacturer, const char *product,
const char *version,
bool uuid_encoded)
const char *version)
{
smbios_have_defaults = true;
smbios_uuid_encoded = uuid_encoded;
SMBIOS_SET_DEFAULT(smbios_type1.manufacturer, manufacturer);
SMBIOS_SET_DEFAULT(smbios_type1.product, product);

2
hw/usb/dev-mtp.c
View File

@ -886,7 +886,7 @@ static MTPData *usb_mtp_get_storage_info(MTPState *s, MTPControl *c)
rc = statvfs(s->root, &buf);
if (rc == 0) {
usb_mtp_add_u64(d, (uint64_t)buf.f_frsize * buf.f_blocks);
usb_mtp_add_u64(d, (uint64_t)buf.f_bavail * buf.f_blocks);
usb_mtp_add_u64(d, (uint64_t)buf.f_frsize * buf.f_bavail);
usb_mtp_add_u32(d, buf.f_ffree);
} else {
usb_mtp_add_u64(d, 0xffffffff);

4
hw/usb/hcd-xhci-nec.c
View File

@ -41,10 +41,6 @@ struct XHCINecState {
static Property nec_xhci_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO),
DEFINE_PROP_BIT("superspeed-ports-first", XHCINecState, flags,
XHCI_FLAG_SS_FIRST, true),
DEFINE_PROP_BIT("force-pcie-endcap", XHCINecState, flags,
XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
DEFINE_PROP_UINT32("intrs", XHCINecState, intrs, XHCI_MAXINTRS),
DEFINE_PROP_UINT32("slots", XHCINecState, slots, XHCI_MAXSLOTS),
DEFINE_PROP_END_OF_LIST(),

4
hw/usb/hcd-xhci-pci.c
View File

@ -148,8 +148,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
PCI_BASE_ADDRESS_MEM_TYPE_64,
&s->xhci.mem);
if (pci_bus_is_express(pci_get_bus(dev)) ||
xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
if (pci_bus_is_express(pci_get_bus(dev))) {
ret = pcie_endpoint_cap_init(dev, 0xa0);
assert(ret > 0);
}
@ -243,7 +242,6 @@ static void qemu_xhci_instance_init(Object *obj)
s->msix = ON_OFF_AUTO_AUTO;
xhci->numintrs = XHCI_MAXINTRS;
xhci->numslots = XHCI_MAXSLOTS;
xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
}
static const TypeInfo qemu_xhci_info = {

42
hw/usb/hcd-xhci.c
View File

@ -541,18 +541,10 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
case USB_SPEED_LOW:
case USB_SPEED_FULL:
case USB_SPEED_HIGH:
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
index = uport->index + xhci->numports_3;
} else {
index = uport->index;
}
index = uport->index + xhci->numports_3;
break;
case USB_SPEED_SUPER:
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
index = uport->index;
} else {
index = uport->index + xhci->numports_2;
}
index = uport->index;
break;
default:
return NULL;
@ -2779,11 +2771,7 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
ret = 0x20425355; /* "USB " */
break;
case 0x28: /* Supported Protocol:08 */
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
} else {
ret = (xhci->numports_2<<8) | 1;
}
ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
break;
case 0x2c: /* Supported Protocol:0c */
ret = 0x00000000; /* reserved */
@ -2795,11 +2783,7 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
ret = 0x20425355; /* "USB " */
break;
case 0x38: /* Supported Protocol:08 */
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
ret = (xhci->numports_3<<8) | 1;
} else {
ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
}
ret = (xhci->numports_3 << 8) | 1;
break;
case 0x3c: /* Supported Protocol:0c */
ret = 0x00000000; /* reserved */
@ -3349,13 +3333,8 @@ static void usb_xhci_init(XHCIState *xhci)
for (i = 0; i < usbports; i++) {
speedmask = 0;
if (i < xhci->numports_2) {
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
port = &xhci->ports[i + xhci->numports_3];
port->portnr = i + 1 + xhci->numports_3;
} else {
port = &xhci->ports[i];
port->portnr = i + 1;
}
port = &xhci->ports[i + xhci->numports_3];
port->portnr = i + 1 + xhci->numports_3;
port->uport = &xhci->uports[i];
port->speedmask =
USB_SPEED_MASK_LOW |
@ -3366,13 +3345,8 @@ static void usb_xhci_init(XHCIState *xhci)
speedmask |= port->speedmask;
}
if (i < xhci->numports_3) {
if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
port = &xhci->ports[i];
port->portnr = i + 1;
} else {
port = &xhci->ports[i + xhci->numports_2];
port->portnr = i + 1 + xhci->numports_2;
}
port = &xhci->ports[i];
port->portnr = i + 1;
port->uport = &xhci->uports[i];
port->speedmask = USB_SPEED_MASK_SUPER;
assert(i < XHCI_MAXPORTS);

4
hw/usb/hcd-xhci.h
View File

@ -36,9 +36,7 @@ typedef struct XHCIStreamContext XHCIStreamContext;
typedef struct XHCIEPContext XHCIEPContext;
enum xhci_flags {
XHCI_FLAG_SS_FIRST = 1,
XHCI_FLAG_FORCE_PCIE_ENDCAP,
XHCI_FLAG_ENABLE_STREAMS,
XHCI_FLAG_ENABLE_STREAMS = 1,
};
typedef enum TRBType {

44
hw/usb/host.h
View File

@ -1,44 +0,0 @@
/*
* Linux host USB redirector
*
* Copyright (c) 2005 Fabrice Bellard
*
* Copyright (c) 2008 Max Krasnyansky
* Support for host device auto connect & disconnect
* Major rewrite to support fully async operation
*
* Copyright 2008 TJ <linux@tjworld.net>
* Added flexible support for /dev/bus/usb /sys/bus/usb/devices in addition
* to the legacy /proc/bus/usb USB device discovery and handling
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef QEMU_USB_HOST_H
#define QEMU_USB_HOST_H
struct USBAutoFilter {
uint32_t bus_num;
uint32_t addr;
char *port;
uint32_t vendor_id;
uint32_t product_id;
};
#endif /* QEMU_USB_HOST_H */

2
hw/virtio/virtio-md-pci.c
View File

@ -37,7 +37,7 @@ void virtio_md_pci_pre_plug(VirtIOMDPCI *vmd, MachineState *ms, Error **errp)
* First, see if we can plug this memory device at all. If that
* succeeds, branch of to the actual hotplug handler.
*/
memory_device_pre_plug(md, ms, NULL, &local_err);
memory_device_pre_plug(md, ms, &local_err);
if (!local_err && bus_handler) {
hotplug_handler_pre_plug(bus_handler, dev, &local_err);
}

2
include/exec/memop.h
View File

@ -161,7 +161,7 @@ static inline MemOp size_memop(unsigned size)
/* Power of 2 up to 8. */
assert((size & (size - 1)) == 0 && size >= 1 && size <= 8);
#endif
return ctz32(size);
return (MemOp)ctz32(size);
}
/* Big endianness from MemOp. */

4
include/exec/memory.h
View File

@ -1837,7 +1837,7 @@ uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr);
*/
void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
int iommu_idx,
IOMMUTLBEvent event);
const IOMMUTLBEvent event);
/**
* memory_region_notify_iommu_one: notify a change in an IOMMU translation
@ -1852,7 +1852,7 @@ void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
* range.
*/
void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
IOMMUTLBEvent *event);
const IOMMUTLBEvent *event);
/**
* memory_region_unmap_iommu_notifier_range: notify a unmap for an IOMMU

3
include/hw/firmware/smbios.h
View File

@ -331,8 +331,7 @@ void smbios_add_usr_blob_size(size_t size);
void smbios_entry_add(QemuOpts *opts, Error **errp);
void smbios_set_cpuid(uint32_t version, uint32_t features);
void smbios_set_defaults(const char *manufacturer, const char *product,
const char *version,
bool uuid_encoded);
const char *version);
void smbios_set_default_processor_family(uint16_t processor_family);
uint8_t *smbios_get_table_legacy(size_t *length, Error **errp);
void smbios_get_tables(MachineState *ms,

22
include/hw/i386/pc.h
View File

@ -74,11 +74,6 @@ typedef struct PCMachineState {
*
* Compat fields:
*
* @enforce_aligned_dimm: check that DIMM's address/size is aligned by
* backend's alignment value if provided
* @acpi_data_size: Size of the chunk of memory at the top of RAM
* for the BIOS ACPI tables and other BIOS
* datastructures.
* @gigabyte_align: Make sure that guest addresses aligned at
* 1Gbyte boundaries get mapped to host
* addresses aligned at 1Gbyte boundaries. This
@ -102,21 +97,16 @@ struct PCMachineClass {
/* ACPI compat: */
bool has_acpi_build;
bool rsdp_in_ram;
int legacy_acpi_table_size;
unsigned acpi_data_size;
int pci_root_uid;
/* SMBIOS compat: */
bool smbios_defaults;
bool smbios_legacy_mode;
bool smbios_uuid_encoded;
SmbiosEntryPointType default_smbios_ep_type;
/* RAM / address space compat: */
bool gigabyte_align;
bool has_reserved_memory;
bool enforce_aligned_dimm;
bool broken_reserved_end;
bool enforce_amd_1tb_hole;
bool isa_bios_alias;
@ -130,9 +120,6 @@ struct PCMachineClass {
/* create kvmclock device even when KVM PV features are not exposed */
bool kvmclock_create_always;
/* resizable acpi blob compat */
bool resizable_acpi_blob;
/*
* whether the machine type implements broken 32-bit address space bound
* check for memory.
@ -312,15 +299,6 @@ extern const size_t pc_compat_2_4_len;
extern GlobalProperty pc_compat_2_3[];
extern const size_t pc_compat_2_3_len;
extern GlobalProperty pc_compat_2_2[];
extern const size_t pc_compat_2_2_len;
extern GlobalProperty pc_compat_2_1[];
extern const size_t pc_compat_2_1_len;
extern GlobalProperty pc_compat_2_0[];
extern const size_t pc_compat_2_0_len;
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
{ \

2
include/hw/intc/intc.h
View File

@ -22,7 +22,7 @@ struct InterruptStatsProviderClass {
*/
bool (*get_statistics)(InterruptStatsProvider *obj, uint64_t **irq_counts,
unsigned int *nb_irqs);
void (*print_info)(InterruptStatsProvider *obj, Monitor *mon);
void (*print_info)(InterruptStatsProvider *obj, GString *buf);
};
#endif

2
include/hw/intc/loongson_ipi.h
View File

@ -34,6 +34,8 @@
OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI)
typedef struct IPICore {
LoongsonIPI *ipi;
MemoryRegion *ipi_mmio_mem;
uint32_t status;
uint32_t en;
uint32_t set;

2
include/hw/mem/memory-device.h
View File

@ -169,7 +169,7 @@ uint64_t get_plugged_memory_size(void);
unsigned int memory_devices_get_reserved_memslots(void);
bool memory_devices_memslot_auto_decision_active(void);
void memory_device_pre_plug(MemoryDeviceState *md, MachineState *ms,
const uint64_t *legacy_align, Error **errp);
Error **errp);
void memory_device_plug(MemoryDeviceState *md, MachineState *ms);
void memory_device_unplug(MemoryDeviceState *md, MachineState *ms);
uint64_t memory_device_get_region_size(const MemoryDeviceState *md,

3
include/hw/mem/pc-dimm.h
View File

@ -66,8 +66,7 @@ struct PCDIMMDeviceClass {
void (*unrealize)(PCDIMMDevice *dimm);
};
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,
const uint64_t *legacy_align, Error **errp);
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine, Error **errp);
void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine);
void pc_dimm_unplug(PCDIMMDevice *dimm, MachineState *machine);
#endif

2
include/hw/pci-host/pnv_phb3.h
View File

@ -40,7 +40,7 @@ void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
int32_t dev_pe);
void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, GString *buf);
/*

2
include/hw/pci-host/pnv_phb4.h
View File

@ -155,7 +155,7 @@ struct PnvPHB4 {
QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;
};
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf);
int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);
void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);

4
include/hw/ppc/pnv_chip.h
View File

@ -151,10 +151,10 @@ struct PnvChipClass {
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
void (*pic_print_info)(PnvChip *chip, GString *buf);
uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
};

2
include/hw/ppc/pnv_psi.h
View File

@ -110,6 +110,6 @@ typedef enum PnvPsiIrq {
#define PSIHB9_IRQ_PSU 13
#define PSIHB9_NUM_IRQS 14
void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
void pnv_psi_pic_print_info(Pnv9Psi *psi, GString *buf);
#endif /* PPC_PNV_PSI_H */

4
include/hw/ppc/pnv_xive.h
View File

@ -93,7 +93,7 @@ struct PnvXiveClass {
DeviceRealize parent_realize;
};
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
void pnv_xive_pic_print_info(PnvXive *xive, GString *buf);
/*
* XIVE2 interrupt controller (POWER10)
@ -163,6 +163,6 @@ typedef struct PnvXive2Class {
DeviceRealize parent_realize;
} PnvXive2Class;
void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon);
void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf);
#endif /* PPC_PNV_XIVE_H */

4
include/hw/ppc/spapr_irq.h
View File

@ -73,7 +73,7 @@ struct SpaprInterruptControllerClass {
/* These methods should only be called on the active intc */
void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
void (*print_info)(SpaprInterruptController *intc, GString *buf);
void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
void *fdt, uint32_t phandle);
int (*post_load)(SpaprInterruptController *intc, int version_id);
@ -85,7 +85,7 @@ int spapr_irq_cpu_intc_create(struct SpaprMachineState *spapr,
PowerPCCPU *cpu, Error **errp);
void spapr_irq_cpu_intc_reset(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_cpu_intc_destroy(struct SpaprMachineState *spapr, PowerPCCPU *cpu);
void spapr_irq_print_info(struct SpaprMachineState *spapr, Monitor *mon);
void spapr_irq_print_info(struct SpaprMachineState *spapr, GString *buf);
void spapr_irq_dt(struct SpaprMachineState *spapr, uint32_t nr_servers,
void *fdt, uint32_t phandle);

4
include/hw/ppc/xics.h
View File

@ -171,8 +171,8 @@ static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
}
void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
void icp_pic_print_info(ICPState *icp, Monitor *mon);
void ics_pic_print_info(ICSState *ics, Monitor *mon);
void icp_pic_print_info(ICPState *icp, GString *buf);
void ics_pic_print_info(ICSState *ics, GString *buf);
void ics_resend(ICSState *ics);
void icp_resend(ICPState *ss);

4
include/hw/ppc/xive.h
View File

@ -314,7 +314,7 @@ static inline bool xive_source_is_asserted(XiveSource *xsrc, uint32_t srcno)
}
void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
Monitor *mon);
GString *buf);
static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
{
@ -528,7 +528,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf);
Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);

8
include/hw/ppc/xive2_regs.h
View File

@ -48,7 +48,7 @@ typedef struct Xive2Eas {
#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon);
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf);
/*
* Event Notifification Descriptor (END)
@ -130,11 +130,11 @@ static inline uint64_t xive2_end_qaddr(Xive2End *end)
(be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
}
void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon);
void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf);
void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
Monitor *mon);
GString *buf);
void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
Monitor *mon);
GString *buf);
/*
* Notification Virtual Processor (NVP)

8
include/hw/ppc/xive_regs.h
View File

@ -167,7 +167,7 @@ typedef struct XiveEAS {
#define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID)
#define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED)
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, GString *buf);
static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
{
@ -261,9 +261,9 @@ static inline uint64_t xive_end_qaddr(XiveEND *end)
be32_to_cpu(end->w3);
}
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf);
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf);
void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf);
/* Notification Virtual Target (NVT) */
typedef struct XiveNVT {

10
include/hw/s390x/storage-keys.h
View File

@ -111,6 +111,16 @@ struct QEMUS390SKeysState {
};
void s390_skeys_init(void);
/**
* @s390_skeys_get: See S390SKeysClass::get_skeys()
*/
int s390_skeys_get(S390SKeysState *ks, uint64_t start_gfn,
uint64_t count, uint8_t *keys);
/**
* @s390_skeys_set: See S390SKeysClass::set_skeys()
*/
int s390_skeys_set(S390SKeysState *ks, uint64_t start_gfn,
uint64_t count, uint8_t *keys);
S390SKeysState *s390_get_skeys_device(void);

6
include/ui/surface.h
View File

@ -45,12 +45,12 @@ void qemu_displaysurface_win32_set_handle(DisplaySurface *surface,
DisplaySurface *qemu_create_displaysurface(int width, int height);
void qemu_free_displaysurface(DisplaySurface *surface);
static inline int is_buffer_shared(DisplaySurface *surface)
static inline int surface_is_allocated(DisplaySurface *surface)
{
return !(surface->flags & QEMU_ALLOCATED_FLAG);
return surface->flags & QEMU_ALLOCATED_FLAG;
}
static inline int is_placeholder(DisplaySurface *surface)
static inline int surface_is_placeholder(DisplaySurface *surface)
{
return surface->flags & QEMU_PLACEHOLDER_FLAG;
}

27
monitor/hmp-cmds.c
View File

@ -26,7 +26,6 @@
#include "qapi/qapi-commands-misc.h"
#include "qapi/qmp/qdict.h"
#include "qemu/cutils.h"
#include "hw/intc/intc.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
@ -82,32 +81,6 @@ void hmp_info_version(Monitor *mon, const QDict *qdict)
qapi_free_VersionInfo(info);
}
static int hmp_info_pic_foreach(Object *obj, void *opaque)
{
InterruptStatsProvider *intc;
InterruptStatsProviderClass *k;
Monitor *mon = opaque;
if (object_dynamic_cast(obj, TYPE_INTERRUPT_STATS_PROVIDER)) {
intc = INTERRUPT_STATS_PROVIDER(obj);
k = INTERRUPT_STATS_PROVIDER_GET_CLASS(obj);
if (k->print_info) {
k->print_info(intc, mon);
} else {
monitor_printf(mon, "Interrupt controller information not available for %s.\n",
object_get_typename(obj));
}
}
return 0;
}
void hmp_info_pic(Monitor *mon, const QDict *qdict)
{
object_child_foreach_recursive(object_get_root(),
hmp_info_pic_foreach, mon);
}
void hmp_quit(Monitor *mon, const QDict *qdict)
{
monitor_suspend(mon);

17
qapi/machine.json
View File

@ -1864,3 +1864,20 @@
{ 'command': 'dumpdtb',
'data': { 'filename': 'str' },
'if': 'CONFIG_FDT' }
##
# @x-query-interrupt-controllers:
#
# Query information on interrupt controller devices
#
# Features:
#
# @unstable: This command is meant for debugging.
#
# Returns: Interrupt controller devices information
#
# Since: 9.1
##
{ 'command': 'x-query-interrupt-controllers',
'returns': 'HumanReadableText',
'features': [ 'unstable' ]}

6
system/memory.c
View File

@ -2006,9 +2006,9 @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
}
void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
IOMMUTLBEvent *event)
const IOMMUTLBEvent *event)
{
IOMMUTLBEntry *entry = &event->entry;
const IOMMUTLBEntry *entry = &event->entry;
hwaddr entry_end = entry->iova + entry->addr_mask;
IOMMUTLBEntry tmp = *entry;
@ -2052,7 +2052,7 @@ void memory_region_unmap_iommu_notifier_range(IOMMUNotifier *notifier)
void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
int iommu_idx,
IOMMUTLBEvent event)
const IOMMUTLBEvent event)
{
IOMMUNotifier *iommu_notifier;

2
target/i386/cpu.c
View File

@ -8281,8 +8281,6 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
false),
DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),

3
target/i386/cpu.h
View File

@ -2108,9 +2108,6 @@ struct ArchCPU {
/* if set, limit maximum value for phys_bits when host_phys_bits is true */
uint8_t host_phys_bits_limit;
/* Stop SMI delivery for migration compatibility with old machines */
bool kvm_no_smi_migration;
/* Forcefully disable KVM PV features not exposed in guest CPUIDs */
bool kvm_pv_enforce_cpuid;

3
target/i386/kvm/kvm-cpu.c
View File

@ -10,7 +10,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "host-cpu.h"
#include "kvm-cpu.h"
#include "qapi/error.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
@ -178,7 +177,7 @@ static PropValue kvm_default_props[] = {
/*
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
*/
void x86_cpu_change_kvm_default(const char *prop, const char *value)
static void x86_cpu_change_kvm_default(const char *prop, const char *value)
{
PropValue *pv;
for (pv = kvm_default_props; pv->prop; pv++) {

41
target/i386/kvm/kvm-cpu.h
View File

@ -1,41 +0,0 @@
/*
* i386 KVM CPU type and functions
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef KVM_CPU_H
#define KVM_CPU_H
#ifdef CONFIG_KVM
/*
* Change the value of a KVM-specific default
*
* If value is NULL, no default will be set and the original
* value from the CPU model table will be kept.
*
* It is valid to call this function only for properties that
* are already present in the kvm_default_props table.
*/
void x86_cpu_change_kvm_default(const char *prop, const char *value);
#else /* !CONFIG_KVM */
#define x86_cpu_change_kvm_default(a, b)
#endif /* CONFIG_KVM */
#endif /* KVM_CPU_H */

7
target/i386/kvm/kvm.c
View File

@ -4474,6 +4474,7 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level)
events.sipi_vector = env->sipi_vector;
if (has_msr_smbase) {
events.flags |= KVM_VCPUEVENT_VALID_SMM;
events.smi.smm = !!(env->hflags & HF_SMM_MASK);
events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
if (kvm_irqchip_in_kernel()) {
@ -4488,12 +4489,6 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level)
events.smi.pending = 0;
events.smi.latched_init = 0;
}
/* Stop SMI delivery on old machine types to avoid a reboot
* on an inward migration of an old VM.
*/
if (!cpu->kvm_no_smi_migration) {
events.flags |= KVM_VCPUEVENT_VALID_SMM;
}
}
if (level >= KVM_PUT_RESET_STATE) {

11
target/s390x/mmu_helper.c
View File

@ -25,7 +25,6 @@
#include "sysemu/tcg.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "trace.h"
#include "hw/hw.h"
#include "hw/s390x/storage-keys.h"
#include "hw/boards.h"
@ -303,7 +302,6 @@ static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
static S390SKeysClass *skeyclass;
static S390SKeysState *ss;
uint8_t key, old_key;
int rc;
/*
* We expect to be called with an absolute address that has already been
@ -341,9 +339,7 @@ static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
*
* TODO: we have races between getting and setting the key.
*/
rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_get_skeys_nonzero(rc);
if (s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key)) {
return;
}
old_key = key;
@ -371,10 +367,7 @@ static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
key |= SK_R;
if (key != old_key) {
rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_set_skeys_nonzero(rc);
}
s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key);
}
}

16
target/s390x/tcg/mem_helper.c
View File

@ -30,7 +30,6 @@
#include "hw/core/tcg-cpu-ops.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "trace.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/s390x/storage-keys.h"
@ -2093,9 +2092,8 @@ uint64_t HELPER(iske)(CPUS390XState *env, uint64_t r2)
}
}
rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
rc = s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_get_skeys_nonzero(rc);
return 0;
}
return key;
@ -2108,7 +2106,6 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1, uint64_t r2)
static S390SKeysClass *skeyclass;
uint64_t addr = wrap_address(env, r2);
uint8_t key;
int rc;
addr = mmu_real2abs(env, addr);
if (!mmu_absolute_addr_valid(addr, false)) {
@ -2124,10 +2121,7 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1, uint64_t r2)
}
key = r1 & 0xfe;
rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_set_skeys_nonzero(rc);
}
s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key);
/*
* As we can only flush by virtual address and not all the entries
* that point to a physical address we have to flush the whole TLB.
@ -2157,18 +2151,16 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
}
}
rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
rc = s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_get_skeys_nonzero(rc);
return 0;
}
re = key & (SK_R | SK_C);
key &= ~SK_R;
rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
rc = s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key);
if (rc) {
trace_set_skeys_nonzero(rc);
return 0;
}
/*

4
target/s390x/trace-events
View File

@ -1,9 +1,5 @@
# See docs/devel/tracing.rst for syntax documentation.
# mmu_helper.c
get_skeys_nonzero(int rc) "SKEY: Call to get_skeys unexpectedly returned %d"
set_skeys_nonzero(int rc) "SKEY: Call to set_skeys unexpectedly returned %d"
# ioinst.c
ioinst(const char *insn) "IOINST: %s"
ioinst_sch_id(const char *insn, int cssid, int ssid, int schid) "IOINST: %s (%x.%x.%04x)"

9
tests/avocado/mem-addr-space-check.py
View File

@ -31,11 +31,10 @@ class MemAddrCheck(QemuSystemTest):
at 4 GiB boundary when "above_4g_mem_size" is 0 (this would be true when
we have 0.5 GiB of VM memory, see pc_q35_init()). This means total
hotpluggable memory size is 60 GiB. Per slot, we reserve 1 GiB of memory
for dimm alignment for all newer machines (see enforce_aligned_dimm
property for pc machines and pc_get_device_memory_range()). That leaves
total hotpluggable actual memory size of 59 GiB. If the VM is started
with 0.5 GiB of memory, maxmem should be set to a maximum value of
59.5 GiB to ensure that the processor can address all memory directly.
for dimm alignment for all machines. That leaves total hotpluggable
actual memory size of 59 GiB. If the VM is started with 0.5 GiB of
memory, maxmem should be set to a maximum value of 59.5 GiB to ensure
that the processor can address all memory directly.
Note that 64-bit pci hole size is 0 in this case. If maxmem is set to
59.6G, QEMU should fail to start with a message "phy-bits are too low".
If maxmem is set to 59.5G with all other QEMU parameters identical, QEMU

62
ui/cocoa.m
View File

@ -296,6 +296,14 @@ static void handleAnyDeviceErrors(Error * err)
{
QEMUScreen screen;
pixman_image_t *pixman_image;
/* The state surrounding mouse grabbing is potentially confusing.
* isAbsoluteEnabled tracks qemu_input_is_absolute() [ie "is the emulated
* pointing device an absolute-position one?"], but is only updated on
* next refresh.
* isMouseGrabbed tracks whether GUI events are directed to the guest;
* it controls whether special keys like Cmd get sent to the guest,
* and whether we capture the mouse when in non-absolute mode.
*/
BOOL isMouseGrabbed;
BOOL isAbsoluteEnabled;
CFMachPortRef eventsTap;
@ -307,17 +315,8 @@ static void handleAnyDeviceErrors(Error * err)
- (void) handleMonitorInput:(NSEvent *)event;
- (bool) handleEvent:(NSEvent *)event;
- (bool) handleEventLocked:(NSEvent *)event;
- (void) setAbsoluteEnabled:(BOOL)tIsAbsoluteEnabled;
/* The state surrounding mouse grabbing is potentially confusing.
* isAbsoluteEnabled tracks qemu_input_is_absolute() [ie "is the emulated
* pointing device an absolute-position one?"], but is only updated on
* next refresh.
* isMouseGrabbed tracks whether GUI events are directed to the guest;
* it controls whether special keys like Cmd get sent to the guest,
* and whether we capture the mouse when in non-absolute mode.
*/
- (void) notifyMouseModeChange;
- (BOOL) isMouseGrabbed;
- (BOOL) isAbsoluteEnabled;
- (QEMUScreen) gscreen;
- (void) raiseAllKeys;
@end
@ -404,6 +403,7 @@ static CGEventRef handleTapEvent(CGEventTapProxy proxy, CGEventType type, CGEven
qkbd_state_switch_console(kbd, con);
dcl.con = con;
register_displaychangelistener(&dcl);
[self notifyMouseModeChange];
[self updateUIInfo];
}
@ -1109,14 +1109,26 @@ static CGEventRef handleTapEvent(CGEventTapProxy proxy, CGEventType type, CGEven
[self raiseAllButtons];
}
- (void) setAbsoluteEnabled:(BOOL)tIsAbsoluteEnabled {
- (void) notifyMouseModeChange {
bool tIsAbsoluteEnabled = bool_with_bql(^{
return qemu_input_is_absolute(dcl.con);
});
if (tIsAbsoluteEnabled == isAbsoluteEnabled) {
return;
}
isAbsoluteEnabled = tIsAbsoluteEnabled;
if (isMouseGrabbed) {
CGAssociateMouseAndMouseCursorPosition(isAbsoluteEnabled);
if (isAbsoluteEnabled) {
[self ungrabMouse];
} else {
CGAssociateMouseAndMouseCursorPosition(isAbsoluteEnabled);
}
}
}
- (BOOL) isMouseGrabbed {return isMouseGrabbed;}
- (BOOL) isAbsoluteEnabled {return isAbsoluteEnabled;}
- (QEMUScreen) gscreen {return screen;}
/*
@ -1791,6 +1803,17 @@ static void addRemovableDevicesMenuItems(void)
qapi_free_BlockInfoList(pointerToFree);
}
static void cocoa_mouse_mode_change_notify(Notifier *notifier, void *data)
{
dispatch_async(dispatch_get_main_queue(), ^{
[cocoaView notifyMouseModeChange];
});
}
static Notifier mouse_mode_change_notifier = {
.notify = cocoa_mouse_mode_change_notify
};
@interface QemuCocoaPasteboardTypeOwner : NSObject<NSPasteboardTypeOwner>
@end
@ -1975,17 +1998,6 @@ static void cocoa_refresh(DisplayChangeListener *dcl)
COCOA_DEBUG("qemu_cocoa: cocoa_refresh\n");
graphic_hw_update(dcl->con);
if (qemu_input_is_absolute(dcl->con)) {
dispatch_async(dispatch_get_main_queue(), ^{
if (![cocoaView isAbsoluteEnabled]) {
if ([cocoaView isMouseGrabbed]) {
[cocoaView ungrabMouse];
}
}
[cocoaView setAbsoluteEnabled:YES];
});
}
if (cbchangecount != [[NSPasteboard generalPasteboard] changeCount]) {
qemu_clipboard_info_unref(cbinfo);
cbinfo = qemu_clipboard_info_new(&cbpeer, QEMU_CLIPBOARD_SELECTION_CLIPBOARD);
@ -2062,6 +2074,8 @@ static void cocoa_display_init(DisplayState *ds, DisplayOptions *opts)
// register vga output callbacks
register_displaychangelistener(&dcl);
qemu_add_mouse_mode_change_notifier(&mouse_mode_change_notifier);
[cocoaView notifyMouseModeChange];
[cocoaView updateUIInfo];
qemu_event_init(&cbevent, false);

3
ui/console.c
View File

@ -1510,7 +1510,8 @@ void qemu_console_resize(QemuConsole *s, int width, int height)
assert(QEMU_IS_GRAPHIC_CONSOLE(s));
if ((s->scanout.kind != SCANOUT_SURFACE ||
(surface && !is_buffer_shared(surface) && !is_placeholder(surface))) &&
(surface && surface_is_allocated(surface) &&
!surface_is_placeholder(surface))) &&
qemu_console_get_width(s, -1) == width &&
qemu_console_get_height(s, -1) == height) {
return;

2
ui/sdl2-2d.c
View File

@ -72,7 +72,7 @@ void sdl2_2d_switch(DisplayChangeListener *dcl,
scon->texture = NULL;
}
if (is_placeholder(new_surface) && qemu_console_get_index(dcl->con)) {
if (surface_is_placeholder(new_surface) && qemu_console_get_index(dcl->con)) {
sdl2_window_destroy(scon);
return;
}

2
ui/sdl2-gl.c
View File

@ -89,7 +89,7 @@ void sdl2_gl_switch(DisplayChangeListener *dcl,
scon->surface = new_surface;
if (is_placeholder(new_surface) && qemu_console_get_index(dcl->con)) {
if (surface_is_placeholder(new_surface) && qemu_console_get_index(dcl->con)) {
qemu_gl_fini_shader(scon->gls);
scon->gls = NULL;
sdl2_window_destroy(scon);

35
util/readline.c
View File

@ -271,6 +271,14 @@ static void readline_hist_add(ReadLineState *rs, const char *cmdline)
rs->hist_entry = -1;
}
static void readline_kill_line(ReadLineState *rs)
{
while (rs->cmd_buf_index > 0) {
readline_backward_char(rs);
readline_delete_char(rs);
}
}
/* completion support */
void readline_add_completion(ReadLineState *rs, const char *str)
@ -405,7 +413,7 @@ void readline_handle_byte(ReadLineState *rs, int ch)
case 12:
readline_clear_screen(rs);
break;
case 10:
case 10: /* fallthrough */
case 13:
rs->cmd_buf[rs->cmd_buf_size] = '\0';
if (!rs->read_password) {
@ -418,6 +426,18 @@ void readline_handle_byte(ReadLineState *rs, int ch)
rs->last_cmd_buf_size = 0;
rs->readline_func(rs->opaque, rs->cmd_buf, rs->readline_opaque);
break;
case 14:
/* ^N Next line in history */
readline_down_char(rs);
break;
case 16:
/* ^P Prev line in history */
readline_up_char(rs);
break;
case 21:
/* ^U Kill backward from point to the beginning of the line. */
readline_kill_line(rs);
break;
case 23:
/* ^W */
readline_backword(rs);
@ -425,7 +445,7 @@ void readline_handle_byte(ReadLineState *rs, int ch)
case 27:
rs->esc_state = IS_ESC;
break;
case 127:
case 127: /* fallthrough */
case 8:
readline_backspace(rs);
break;
@ -452,11 +472,11 @@ void readline_handle_byte(ReadLineState *rs, int ch)
break;
case IS_CSI:
switch (ch) {
case 'A':
case 'A': /* fallthrough */
case 'F':
readline_up_char(rs);
break;
case 'B':
case 'B': /* fallthrough */
case 'E':
readline_down_char(rs);
break;
@ -480,12 +500,15 @@ void readline_handle_byte(ReadLineState *rs, int ch)
case 4:
readline_eol(rs);
break;
default:
break;
}
break;
default:
break;
}
rs->esc_state = IS_NORM;
/* fallthrough */
the_end:
break;
case IS_SS3:
@ -496,9 +519,13 @@ void readline_handle_byte(ReadLineState *rs, int ch)
case 'H':
readline_bol(rs);
break;
default:
break;
}
rs->esc_state = IS_NORM;
break;
default:
break;
}
readline_update(rs);
}