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Xilinx queue: 

hw/dma: Add error handling for loading descriptions failing (Fea Wang)
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Merge tag 'edgar/xilinx-queue-2024-06-17.for-upstream' of https://gitlab.com/edgar.iglesias/qemu into staging

Xilinx queue:

hw/dma: Add error handling for loading descriptions failing (Fea Wang)

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# gpg: Signature made Tue 18 Jun 2024 05:54:18 AM PDT
# gpg:                using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown]
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full]

* tag 'edgar/xilinx-queue-2024-06-17.for-upstream' of https://gitlab.com/edgar.iglesias/qemu:
  hw/net: Fix the transmission return size
  hw/dma: Add a trace log for a description loading failure
  hw/dma: Enhance error handling in loading description

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-06-18 13:08:01 -07:00
parent 900536d3e9 3a6d374b75
commit 223696363b
3 changed files with 33 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/dma/trace-events
View File

@ -44,3 +44,6 @@ pl330_debug_exec_stall(void) "stall of debug instruction not implemented"
pl330_iomem_write(uint32_t offset, uint32_t value) "addr: 0x%08"PRIx32" data: 0x%08"PRIx32
pl330_iomem_write_clr(int i) "event interrupt lowered %d"
pl330_iomem_read(uint32_t addr, uint32_t data) "addr: 0x%08"PRIx32" data: 0x%08"PRIx32
# xilinx_axidma.c
xilinx_axidma_loading_desc_fail(uint32_t res) "error:%u"

33
hw/dma/xilinx_axidma.c
View File

@ -36,6 +36,7 @@
#include "sysemu/dma.h"
#include "hw/stream.h"
#include "qom/object.h"
#include "trace.h"
#define D(x)
@ -71,8 +72,11 @@ enum {
enum {
DMASR_HALTED = 1,
DMASR_IDLE = 2,
DMASR_SLVERR = 1 << 5,
DMASR_DECERR = 1 << 6,
DMASR_IOC_IRQ = 1 << 12,
DMASR_DLY_IRQ = 1 << 13,
DMASR_ERR_IRQ = 1 << 14,
DMASR_IRQ_MASK = 7 << 12
};
@ -190,17 +194,34 @@ static inline int streamid_from_addr(hwaddr addr)
return sid;
}
static void stream_desc_load(struct Stream *s, hwaddr addr)
static MemTxResult stream_desc_load(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
MemTxResult result = address_space_read(&s->dma->as,
addr, MEMTXATTRS_UNSPECIFIED,
d, sizeof *d);
if (result != MEMTX_OK) {
trace_xilinx_axidma_loading_desc_fail(result);
if (result == MEMTX_DECODE_ERROR) {
s->regs[R_DMASR] |= DMASR_DECERR;
} else {
s->regs[R_DMASR] |= DMASR_SLVERR;
}
s->regs[R_DMACR] &= ~DMACR_RUNSTOP;
s->regs[R_DMASR] |= DMASR_HALTED;
s->regs[R_DMASR] |= DMASR_ERR_IRQ;
return result;
}
/* Convert from LE into host endianness. */
d->buffer_address = le64_to_cpu(d->buffer_address);
d->nxtdesc = le64_to_cpu(d->nxtdesc);
d->control = le32_to_cpu(d->control);
d->status = le32_to_cpu(d->status);
return result;
}
static void stream_desc_store(struct Stream *s, hwaddr addr)
@ -279,7 +300,9 @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
}
while (1) {
stream_desc_load(s, s->regs[R_CURDESC]);
if (MEMTX_OK != stream_desc_load(s, s->regs[R_CURDESC])) {
break;
}
if (s->desc.status & SDESC_STATUS_COMPLETE) {
s->regs[R_DMASR] |= DMASR_HALTED;
@ -336,7 +359,9 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
}
while (len) {
stream_desc_load(s, s->regs[R_CURDESC]);
if (MEMTX_OK != stream_desc_load(s, s->regs[R_CURDESC])) {
break;
}
if (s->desc.status & SDESC_STATUS_COMPLETE) {
s->regs[R_DMASR] |= DMASR_HALTED;

2
hw/net/xilinx_axienet.c
View File

@ -847,7 +847,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
axienet_eth_rx_notify(s);
enet_update_irq(s);
return size;
return s->rxpos;
}
static size_t