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target-arm queue: 

* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
  * docs/system/arm: Fix broken links and missing feature names
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Merge tag 'pull-target-arm-20241126' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
 * docs/system/arm: Fix broken links and missing feature names

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# gpg: Signature made Tue 26 Nov 2024 17:01:41 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241126' of https://git.linaro.org/people/pmaydell/qemu-arm:
  docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
  docs/system/arm/fby35: update link to product page
  docs/system/arm/: add FEAT_DoubleLock
  docs/system/arm/: add FEAT_MTE_ASYNC
  target/arm/tcg/: fix typo in FEAT name
  docs/system/arm/emulation: add FEAT_SSBS2
  docs/system/arm/emulation: fix typo in feature name
  docs/system/arm/emulation: mention armv9
  target/arm/tcg/cpu32.c: swap ATCM and BTCM register names

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-11-26 17:02:44 +00:00
parent ba54a7e6b8 d8790ead55
commit 7cbea81618
4 changed files with 15 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
docs/system/arm/aspeed.rst
View File

@ -1,5 +1,5 @@
Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
======================================================================================================================================================================================================================================================================================================================================================================================================== ==================================================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the Aspeed evaluation boards. They are based on different releases of the
@ -15,7 +15,8 @@ AST2400 SoC based machines :
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
- ``supermicrox11-bmc`` Supermicro X11 BMC - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
AST2500 SoC based machines : AST2500 SoC based machines :

11
docs/system/arm/emulation.rst
View File

@ -3,8 +3,8 @@
A-profile CPU architecture support A-profile CPU architecture support
================================== ==================================
QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
Armv8 versions of the A-profile architecture. It also has support for Armv8 and Armv9 versions of the A-profile architecture. It also has support for
the following architecture extensions: the following architecture extensions:
- FEAT_AA32BF16 (AArch32 BFloat16 instructions) - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
@ -37,6 +37,7 @@ the following architecture extensions:
- FEAT_CSV3 (Cache speculation variant 3) - FEAT_CSV3 (Cache speculation variant 3)
- FEAT_DGH (Data gathering hint) - FEAT_DGH (Data gathering hint)
- FEAT_DIT (Data Independent Timing instructions) - FEAT_DIT (Data Independent Timing instructions)
- FEAT_DoubleLock (Double Lock)
- FEAT_DPB (DC CVAP instruction) - FEAT_DPB (DC CVAP instruction)
- FEAT_DPB2 (DC CVADP instruction) - FEAT_DPB2 (DC CVADP instruction)
- FEAT_Debugv8p1 (Debug with VHE) - FEAT_Debugv8p1 (Debug with VHE)
@ -88,12 +89,13 @@ the following architecture extensions:
- FEAT_LSE2 (Large System Extensions v2) - FEAT_LSE2 (Large System Extensions v2)
- FEAT_LVA (Large Virtual Address space) - FEAT_LVA (Large Virtual Address space)
- FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEnd (Mixed-endian support)
- FEAT_MixdEndEL0 (Mixed-endian support at EL0) - FEAT_MixedEndEL0 (Mixed-endian support at EL0)
- FEAT_MOPS (Standardization of memory operations) - FEAT_MOPS (Standardization of memory operations)
- FEAT_MTE (Memory Tagging Extension) - FEAT_MTE (Memory Tagging Extension)
- FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension)
- FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_MTE3 (MTE Asymmetric Fault Handling)
- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) - FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
- FEAT_NMI (Non-maskable Interrupt) - FEAT_NMI (Non-maskable Interrupt)
- FEAT_NV (Nested Virtualization) - FEAT_NV (Nested Virtualization)
- FEAT_NV2 (Enhanced nested virtualization support) - FEAT_NV2 (Enhanced nested virtualization support)
@ -137,6 +139,7 @@ the following architecture extensions:
- FEAT_SVE2 (Scalable Vector Extension version 2) - FEAT_SVE2 (Scalable Vector Extension version 2)
- FEAT_SPECRES (Speculation restriction instructions) - FEAT_SPECRES (Speculation restriction instructions)
- FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS (Speculative Store Bypass Safe)
- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
@ -153,7 +156,7 @@ the following architecture extensions:
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
For information on the specifics of these extensions, please refer For information on the specifics of these extensions, please refer
to the `Armv8-A Arm Architecture Reference Manual to the `Arm Architecture Reference Manual for A-profile architecture
<https://developer.arm.com/documentation/ddi0487/latest>`_. <https://developer.arm.com/documentation/ddi0487/latest>`_.
When a specific named CPU is being emulated, only those features which When a specific named CPU is being emulated, only those features which

2
docs/system/arm/fby35.rst
View File

@ -12,7 +12,7 @@ include various compute accelerators (video, inferencing, etc). At the moment,
only the first server slot's BIC is included. only the first server slot's BIC is included.
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
for an example. for an example.
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC

6
target/arm/tcg/cpu32.c
View File

@ -71,7 +71,7 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_mmfr5 = t; cpu->isar.id_mmfr5 = t;
t = cpu->isar.id_pfr0; t = cpu->isar.id_pfr0;
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t; cpu->isar.id_pfr0 = t;
@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj)
static const ARMCPRegInfo cortexr5_cp_reginfo[] = { static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */ /* Dummy the TCM region regs for the moment */
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST }, .access = PL1_RW, .type = ARM_CP_CONST },
{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST }, .access = PL1_RW, .type = ARM_CP_CONST },
{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },