From a0dfe58acda236ebb4ebf292b1c5980487d6d046 Mon Sep 17 00:00:00 2001 From: Michael Tokarev Date: Tue, 26 Nov 2024 16:12:09 +0000 Subject: [PATCH 1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names According to Cortex-R5 r1p2 manual, register with opcode2=0 is BTCM and with opcode2=1 is ATCM, - exactly the opposite from how qemu labels them. Just swap the labels to avoid confusion, - both registers are implemented as always-zero. Signed-off-by: Michael Tokarev Reviewed-by: Richard Henderson Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru Signed-off-by: Peter Maydell --- target/arm/tcg/cpu32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 20c2737f17..2a77701f8d 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj) static const ARMCPRegInfo cortexr5_cp_reginfo[] = { /* Dummy the TCM region regs for the moment */ - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST }, - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_CONST }, { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, From c36fb96d9da523bb706cb6140dfe8ed4276c3165 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:38 -0800 Subject: [PATCH 2/9] docs/system/arm/emulation: mention armv9 Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index a2a388f091..2956c22a1b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -3,8 +3,8 @@ A-profile CPU architecture support ================================== -QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and -Armv8 versions of the A-profile architecture. It also has support for +QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7, +Armv8 and Armv9 versions of the A-profile architecture. It also has support for the following architecture extensions: - FEAT_AA32BF16 (AArch32 BFloat16 instructions) @@ -153,7 +153,7 @@ the following architecture extensions: - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) For information on the specifics of these extensions, please refer -to the `Armv8-A Arm Architecture Reference Manual +to the `Arm Architecture Reference Manual for A-profile architecture `_. When a specific named CPU is being emulated, only those features which From 75c1f8d1c981c9f9abaea00c94864ee18bf8348c Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:39 -0800 Subject: [PATCH 3/9] docs/system/arm/emulation: fix typo in feature name Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2956c22a1b..af613b9c8b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -88,7 +88,7 @@ the following architecture extensions: - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) - FEAT_MixedEnd (Mixed-endian support) -- FEAT_MixdEndEL0 (Mixed-endian support at EL0) +- FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) From 4fc5ec4c9c79b14abc50ec7f4827930e99302413 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:40 -0800 Subject: [PATCH 4/9] docs/system/arm/emulation: add FEAT_SSBS2 We implemented this at the same times as FEAT_SSBS, but forgot to list it in the documentation. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org Reviewed-by: Peter Maydell [PMM: improve commit message] Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index af613b9c8b..50d0250b1e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -137,6 +137,7 @@ the following architecture extensions: - FEAT_SVE2 (Scalable Vector Extension version 2) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) +- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) From 2b65ea865955275bdb7e55685af04bc7cf29d236 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:41 -0800 Subject: [PATCH 5/9] target/arm/tcg/: fix typo in FEAT name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/cpu32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2a77701f8d..2ad2182525 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -71,7 +71,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr5 = t; t = cpu->isar.id_pfr0; - t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 = t; From 7ddaf0ea2a5713a30bb73147b87bd76fb6421614 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:42 -0800 Subject: [PATCH 6/9] docs/system/arm/: add FEAT_MTE_ASYNC We already implement FEAT_MTE_ASYNC; we just forgot to list it in the documentation. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org [PMM: expand commit message] Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 50d0250b1e..47f5123a31 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -94,6 +94,7 @@ the following architecture extensions: - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) +- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault) - FEAT_NMI (Non-maskable Interrupt) - FEAT_NV (Nested Virtualization) - FEAT_NV2 (Enhanced nested virtualization support) From e8319a32271c0a8a25f2a6a55b6612629634b4cd Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:43 -0800 Subject: [PATCH 7/9] docs/system/arm/: add FEAT_DoubleLock We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when the ID registers call for it. This feature is actually one that must *not* be implemented in v9.0, but since our documentation lists everything we can emulate, we should include FEAT_DoubleLock in the list. Signed-off-by: Pierrick Bouvier Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org Reviewed-by: Peter Maydell [PMM: expand commit message] Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 47f5123a31..38534dcdd3 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -37,6 +37,7 @@ the following architecture extensions: - FEAT_CSV3 (Cache speculation variant 3) - FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) +- FEAT_DoubleLock (Double Lock) - FEAT_DPB (DC CVAP instruction) - FEAT_DPB2 (DC CVADP instruction) - FEAT_Debugv8p1 (Debug with VHE) From 23055b131072730d4a16a48ef2449cc0ad5f4ed4 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:44 -0800 Subject: [PATCH 8/9] docs/system/arm/fby35: update link to product page MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/fby35.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst index 742b887d44..bf6da6baa2 100644 --- a/docs/system/arm/fby35.rst +++ b/docs/system/arm/fby35.rst @@ -12,7 +12,7 @@ include various compute accelerators (video, inferencing, etc). At the moment, only the first server slot's BIC is included. Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds -can be fit into a chassis. See `here `__ +can be fit into a chassis. See `here `__ for an example. In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC From d8790ead55a2ef1e65332ebec63ae3c5db598942 Mon Sep 17 00:00:00 2001 From: Pierrick Bouvier Date: Fri, 22 Nov 2024 14:50:49 -0800 Subject: [PATCH 9/9] docs/system/arm/aspeed: add missing model supermicrox11spi-bmc Signed-off-by: Pierrick Bouvier Reviewed-by: Andrew Jeffery Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 2e9ba12f7a..d17fe7a4fc 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,5 +1,5 @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) -======================================================================================================================================================================================================================================================================================================================================================================================================== +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) +================================================================================================================================================================================================================================================================================================================================================================================================================================== The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the @@ -15,7 +15,8 @@ AST2400 SoC based machines : - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC - ``quanta-q71l-bmc`` OpenBMC Quanta BMC -- ``supermicrox11-bmc`` Supermicro X11 BMC +- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S) +- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176) AST2500 SoC based machines :