mirror of https://github.com/xemu-project/xemu.git
target-arm queue:
* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names * docs/system/arm: Fix broken links and missing feature names -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmdF/vUZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3m4VD/95q5242ldAFCDj3pftP7tZ DCdY+AZZiUc+2puCjUlxCaKyXkTr4ifwUe79RStbatW80JxGJbJHeRK1VA4dNlPD trl+6fN5gS6VpvIpkfS92qH8VDF2XfygPIjisCUf7MIsJCgLa9XEJ8lQvHcxgT2v VSYholfKrU5bsS5UIuMC+cNjTaLLgwEW0RSqvo0/ZTnOZgfLJk6PD938WV6kbHoA 6qbwLgoKoSaZDxmnKAxqMMsnMPAnYE4mSSQsawwa92f5zj7p6Pz9FjDBGRuBnBan JeSyW9C7X555BT5YxluEqicsOK+xGg58y3QrQuDRwXHUO3gCMBMS+CGapNPhA7rN sTIILk2JsGuer4w6Gz/xOIr/nyqufejJd91AVrfC782UXqfi1Gb/xYfsLOz4xSr5 TzvXMmD/u0yna5OLc6S+eFY5+qWvuIUwty4OTBPN/txd+pzDnsdISMaqXfDl0Czj idUVN+xEVBhKvHCFcFt15iwSMgoQ62Vyh5EWyZ5kaeC/w5L6rt+B/Es3XBnx2XSi CTU6FQHPrgqbbjF9PIOPq8lavbXTKZ/KsXhCCQ02zh9wLG9JH9nnGLWB7uEIDd8N yrd5qp47FooJYisZcfI9SmAU7tcYHbaNmFmGTA2b9UPJW8SvNmzSdhKV/nPFV9JK MwJwXffOhI8kXobUrJo03A== =yUs5 -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20241126' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm/tcg/cpu32.c: swap ATCM and BTCM register names * docs/system/arm: Fix broken links and missing feature names # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmdF/vUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3m4VD/95q5242ldAFCDj3pftP7tZ # DCdY+AZZiUc+2puCjUlxCaKyXkTr4ifwUe79RStbatW80JxGJbJHeRK1VA4dNlPD # trl+6fN5gS6VpvIpkfS92qH8VDF2XfygPIjisCUf7MIsJCgLa9XEJ8lQvHcxgT2v # VSYholfKrU5bsS5UIuMC+cNjTaLLgwEW0RSqvo0/ZTnOZgfLJk6PD938WV6kbHoA # 6qbwLgoKoSaZDxmnKAxqMMsnMPAnYE4mSSQsawwa92f5zj7p6Pz9FjDBGRuBnBan # JeSyW9C7X555BT5YxluEqicsOK+xGg58y3QrQuDRwXHUO3gCMBMS+CGapNPhA7rN # sTIILk2JsGuer4w6Gz/xOIr/nyqufejJd91AVrfC782UXqfi1Gb/xYfsLOz4xSr5 # TzvXMmD/u0yna5OLc6S+eFY5+qWvuIUwty4OTBPN/txd+pzDnsdISMaqXfDl0Czj # idUVN+xEVBhKvHCFcFt15iwSMgoQ62Vyh5EWyZ5kaeC/w5L6rt+B/Es3XBnx2XSi # CTU6FQHPrgqbbjF9PIOPq8lavbXTKZ/KsXhCCQ02zh9wLG9JH9nnGLWB7uEIDd8N # yrd5qp47FooJYisZcfI9SmAU7tcYHbaNmFmGTA2b9UPJW8SvNmzSdhKV/nPFV9JK # MwJwXffOhI8kXobUrJo03A== # =yUs5 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 Nov 2024 17:01:41 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20241126' of https://git.linaro.org/people/pmaydell/qemu-arm: docs/system/arm/aspeed: add missing model supermicrox11spi-bmc docs/system/arm/fby35: update link to product page docs/system/arm/: add FEAT_DoubleLock docs/system/arm/: add FEAT_MTE_ASYNC target/arm/tcg/: fix typo in FEAT name docs/system/arm/emulation: add FEAT_SSBS2 docs/system/arm/emulation: fix typo in feature name docs/system/arm/emulation: mention armv9 target/arm/tcg/cpu32.c: swap ATCM and BTCM register names Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7cbea81618
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@ -1,5 +1,5 @@
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Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
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========================================================================================================================================================================================================================================================================================================================================================================================================
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Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
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==================================================================================================================================================================================================================================================================================================================================================================================================================================
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The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
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Aspeed evaluation boards. They are based on different releases of the
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@ -15,7 +15,8 @@ AST2400 SoC based machines :
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- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
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- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
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- ``supermicrox11-bmc`` Supermicro X11 BMC
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- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
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- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
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AST2500 SoC based machines :
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@ -3,8 +3,8 @@
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A-profile CPU architecture support
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==================================
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QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
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Armv8 versions of the A-profile architecture. It also has support for
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QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
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Armv8 and Armv9 versions of the A-profile architecture. It also has support for
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the following architecture extensions:
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- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
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@ -37,6 +37,7 @@ the following architecture extensions:
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- FEAT_CSV3 (Cache speculation variant 3)
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- FEAT_DGH (Data gathering hint)
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- FEAT_DIT (Data Independent Timing instructions)
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- FEAT_DoubleLock (Double Lock)
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- FEAT_DPB (DC CVAP instruction)
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- FEAT_DPB2 (DC CVADP instruction)
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- FEAT_Debugv8p1 (Debug with VHE)
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@ -88,12 +89,13 @@ the following architecture extensions:
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- FEAT_LSE2 (Large System Extensions v2)
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- FEAT_LVA (Large Virtual Address space)
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- FEAT_MixedEnd (Mixed-endian support)
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- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
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- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
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- FEAT_MOPS (Standardization of memory operations)
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- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
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- FEAT_MTE3 (MTE Asymmetric Fault Handling)
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- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
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- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
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- FEAT_NMI (Non-maskable Interrupt)
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- FEAT_NV (Nested Virtualization)
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- FEAT_NV2 (Enhanced nested virtualization support)
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@ -137,6 +139,7 @@ the following architecture extensions:
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- FEAT_SVE2 (Scalable Vector Extension version 2)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
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- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
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- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
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- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
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@ -153,7 +156,7 @@ the following architecture extensions:
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- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
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For information on the specifics of these extensions, please refer
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to the `Armv8-A Arm Architecture Reference Manual
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to the `Arm Architecture Reference Manual for A-profile architecture
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<https://developer.arm.com/documentation/ddi0487/latest>`_.
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When a specific named CPU is being emulated, only those features which
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@ -12,7 +12,7 @@ include various compute accelerators (video, inferencing, etc). At the moment,
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only the first server slot's BIC is included.
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Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
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can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
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can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
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for an example.
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In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
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@ -71,7 +71,7 @@ void aa32_max_features(ARMCPU *cpu)
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cpu->isar.id_mmfr5 = t;
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t = cpu->isar.id_pfr0;
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t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
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t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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cpu->isar.id_pfr0 = t;
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@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj)
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static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
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/* Dummy the TCM region regs for the moment */
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{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
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.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
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