target/ppc: add helper to write per-LPAR SPRs

An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-05-27 03:17:38 +10:00
parent 1cbcbcb8d6
commit 5fa7efe473
2 changed files with 30 additions and 0 deletions

View File

@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn);

View File

@ -473,6 +473,34 @@ void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
spr_store_dump_spr(sprn);
}
void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0;
if (!(ctx->flags & POWERPC_FLAG_SMT)) {
spr_write_generic32(ctx, sprn, gprn);
return;
}
if (!gen_serialize(ctx)) {
return;
}
t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0);
spr_store_dump_spr(sprn);
}
void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn)
{
if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
spr_core_write_generic(ctx, sprn, gprn);
} else {
spr_write_generic(ctx, sprn, gprn);
}
}
static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
{
/* This does not implement >1 thread */