mirror of https://github.com/xemu-project/xemu.git
target/ppc: add helper to write per-LPAR SPRs
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means per-thread or per-core, depending on 1LPAR mode. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
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void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
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void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
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void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
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void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn);
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void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn);
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void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
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void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
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void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn);
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@ -473,6 +473,34 @@ void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
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spr_store_dump_spr(sprn);
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}
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void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv t0;
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if (!(ctx->flags & POWERPC_FLAG_SMT)) {
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spr_write_generic32(ctx, sprn, gprn);
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return;
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}
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if (!gen_serialize(ctx)) {
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return;
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}
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t0 = tcg_temp_new();
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tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
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gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0);
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spr_store_dump_spr(sprn);
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}
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void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn)
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{
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if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
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spr_core_write_generic(ctx, sprn, gprn);
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} else {
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spr_write_generic(ctx, sprn, gprn);
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}
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}
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static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
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{
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/* This does not implement >1 thread */
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