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target/ppc: Add PPR32 SPR 

PPR32 provides access to the upper half of PPR.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-09-11 13:02:35 +10:00
parent e89294b27e
commit 1cbcbcb8d6
4 changed files with 39 additions and 0 deletions
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1
target/ppc/cpu.h
View File

@ -2120,6 +2120,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_POWER_MMCRS (0x37E)
#define SPR_WORT (0x37F)
#define SPR_PPR (0x380)
#define SPR_PPR32 (0x382)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
#define SPR_750_GQR1 (0x391)

12
target/ppc/cpu_init.c
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@ -5606,6 +5606,14 @@ static void register_HEIR64_spr(CPUPPCState *env)
0x00000000);
}
static void register_power7_common_sprs(CPUPPCState *env)
{
spr_register(env, SPR_PPR32, "PPR32",
&spr_read_ppr32, &spr_write_ppr32,
&spr_read_ppr32, &spr_write_ppr32,
0x00000000);
}
static void register_power8_tce_address_control_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
@ -6101,6 +6109,7 @@ static void init_proc_POWER7(CPUPPCState *env)
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
register_power7_common_sprs(env);
register_power7_book4_sprs(env);
/* env variables */
@ -6247,6 +6256,7 @@ static void init_proc_POWER8(CPUPPCState *env)
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);
@ -6414,6 +6424,7 @@ static void init_proc_POWER9(CPUPPCState *env)
register_power6_common_sprs(env);
register_HEIR32_spr(env);
register_power6_dbg_sprs(env);
register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);
@ -6608,6 +6619,7 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power6_common_sprs(env);
register_HEIR64_spr(env);
register_power6_dbg_sprs(env);
register_power7_common_sprs(env);
register_power8_tce_address_control_sprs(env);
register_power8_ids_sprs(env);
register_power8_ebb_sprs(env);

2
target/ppc/spr_common.h
View File

@ -203,6 +203,8 @@ void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn);
void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn);
void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn);
#endif
void register_low_BATs(CPUPPCState *env);

24
target/ppc/translate.c
View File

@ -1352,6 +1352,30 @@ void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
gen_load_spr(t0, sprn + 16);
tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
}
/* The PPR32 SPR accesses the upper 32-bits of PPR */
void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn)
{
gen_load_spr(cpu_gpr[gprn], SPR_PPR);
tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32);
spr_load_dump_spr(SPR_PPR);
}
void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
/*
* Don't clobber the low 32-bits of the PPR. These are all reserved bits
* but TCG does implement them, so it would be surprising to zero them
* here. "Priority nops" are similarly careful not to clobber reserved
* bits.
*/
gen_load_spr(t0, SPR_PPR);
tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32);
gen_store_spr(SPR_PPR, t0);
spr_store_dump_spr(SPR_PPR);
}
#endif
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \