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target/arm: Convert TBL, TBX to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1141,3 +1141,7 @@ FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd
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EXT_d 0010 1110 00 0 rm:5 00 imm:3 0 rn:5 rd:5
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EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5
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# Advanced SIMD Table Lookup
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TBL_TBX 0 q:1 00 1110 000 rm:5 0 len:2 tbx:1 00 rn:5 rd:5
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@ -4680,6 +4680,20 @@ static bool trans_EXTR(DisasContext *s, arg_extract *a)
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return true;
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}
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static bool trans_TBL_TBX(DisasContext *s, arg_TBL_TBX *a)
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{
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if (fp_access_check(s)) {
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int len = (a->len + 1) * 16;
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tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),
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vec_full_reg_offset(s, a->rm), tcg_env,
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a->q ? 16 : 8, vec_full_reg_size(s),
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(len << 6) | (a->tbx << 5) | a->rn,
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gen_helper_simd_tblx);
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}
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return true;
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}
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/*
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* Cryptographic AES, SHA, SHA512
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*/
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@ -8938,38 +8952,6 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
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}
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}
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/* TBL/TBX
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* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
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* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
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* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
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* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
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*/
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static void disas_simd_tb(DisasContext *s, uint32_t insn)
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{
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int op2 = extract32(insn, 22, 2);
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int is_q = extract32(insn, 30, 1);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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int is_tbx = extract32(insn, 12, 1);
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int len = (extract32(insn, 13, 2) + 1) * 16;
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if (op2 != 0) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rm), tcg_env,
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is_q ? 16 : 8, vec_full_reg_size(s),
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(len << 6) | (is_tbx << 5) | rn,
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gen_helper_simd_tblx);
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}
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/* ZIP/UZP/TRN
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* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
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* +---+---+-------------+------+---+------+---+------------------+------+
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@ -11834,7 +11816,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
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/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
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{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
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{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },
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{ 0x0e000000, 0xbf208c00, disas_simd_tb },
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{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
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{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
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{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
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