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target/arm: Convert EXT to decodetree
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
88f26451c9
commit
9c8f7da04b
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@ -1136,3 +1136,8 @@ FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..... @rrrr_hsd
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FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd
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FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd
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FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd
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# Advanced SIMD Extract
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EXT_d 0010 1110 00 0 rm:5 00 imm:3 0 rn:5 rd:5
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EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5
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@ -6582,6 +6582,54 @@ static bool trans_FCSEL(DisasContext *s, arg_FCSEL *a)
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return true;
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}
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/*
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* Advanced SIMD Extract
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*/
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static bool trans_EXT_d(DisasContext *s, arg_EXT_d *a)
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{
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if (fp_access_check(s)) {
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TCGv_i64 lo = read_fp_dreg(s, a->rn);
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if (a->imm != 0) {
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TCGv_i64 hi = read_fp_dreg(s, a->rm);
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tcg_gen_extract2_i64(lo, lo, hi, a->imm * 8);
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}
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write_fp_dreg(s, a->rd, lo);
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}
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return true;
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}
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static bool trans_EXT_q(DisasContext *s, arg_EXT_q *a)
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{
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TCGv_i64 lo, hi;
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int pos = (a->imm & 7) * 8;
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int elt = a->imm >> 3;
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if (!fp_access_check(s)) {
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return true;
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}
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lo = tcg_temp_new_i64();
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hi = tcg_temp_new_i64();
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read_vec_element(s, lo, a->rn, elt, MO_64);
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elt++;
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read_vec_element(s, hi, elt & 2 ? a->rm : a->rn, elt & 1, MO_64);
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elt++;
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if (pos != 0) {
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TCGv_i64 hh = tcg_temp_new_i64();
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tcg_gen_extract2_i64(lo, lo, hi, pos);
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read_vec_element(s, hh, a->rm, elt & 1, MO_64);
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tcg_gen_extract2_i64(hi, hi, hh, pos);
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}
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write_vec_element(s, lo, a->rd, 0, MO_64);
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write_vec_element(s, hi, a->rd, 1, MO_64);
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clear_vec_high(s, true, a->rd);
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return true;
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}
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/*
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* Floating-point data-processing (3 source)
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*/
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@ -8890,78 +8938,6 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
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}
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}
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/* EXT
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* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
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* +---+---+-------------+-----+---+------+---+------+---+------+------+
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* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
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* +---+---+-------------+-----+---+------+---+------+---+------+------+
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*/
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static void disas_simd_ext(DisasContext *s, uint32_t insn)
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{
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int is_q = extract32(insn, 30, 1);
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int op2 = extract32(insn, 22, 2);
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int imm4 = extract32(insn, 11, 4);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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int pos = imm4 << 3;
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TCGv_i64 tcg_resl, tcg_resh;
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if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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tcg_resh = tcg_temp_new_i64();
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tcg_resl = tcg_temp_new_i64();
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/* Vd gets bits starting at pos bits into Vm:Vn. This is
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* either extracting 128 bits from a 128:128 concatenation, or
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* extracting 64 bits from a 64:64 concatenation.
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*/
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if (!is_q) {
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read_vec_element(s, tcg_resl, rn, 0, MO_64);
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if (pos != 0) {
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read_vec_element(s, tcg_resh, rm, 0, MO_64);
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tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos);
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}
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} else {
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TCGv_i64 tcg_hh;
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typedef struct {
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int reg;
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int elt;
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} EltPosns;
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EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} };
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EltPosns *elt = eltposns;
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if (pos >= 64) {
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elt++;
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pos -= 64;
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}
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read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);
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elt++;
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read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);
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elt++;
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if (pos != 0) {
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tcg_gen_extract2_i64(tcg_resl, tcg_resl, tcg_resh, pos);
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tcg_hh = tcg_temp_new_i64();
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read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);
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tcg_gen_extract2_i64(tcg_resh, tcg_resh, tcg_hh, pos);
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}
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}
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write_vec_element(s, tcg_resl, rd, 0, MO_64);
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if (is_q) {
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write_vec_element(s, tcg_resh, rd, 1, MO_64);
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}
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clear_vec_high(s, is_q, rd);
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}
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/* TBL/TBX
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* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
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* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
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@ -11860,7 +11836,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },
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{ 0x0e000000, 0xbf208c00, disas_simd_tb },
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{ 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
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{ 0x2e000000, 0xbf208400, disas_simd_ext },
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{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
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{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
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{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
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