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target/arm: Support MSR access to ALLINT 

Support ALLINT msr access as follow:
	mrs <xt>, ALLINT	// read allint
	msr ALLINT, <xt>	// write allint with imm

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:32:57 +01:00 committed by Peter Maydell
parent cbf817a2ff
commit 5c21697461
1 changed files with 35 additions and 0 deletions
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35
target/arm/helper.c
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@ -7500,6 +7500,37 @@ static const ARMCPRegInfo rme_mte_reginfo[] = {
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NOP },
};
static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT);
}
static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return env->pstate & PSTATE_ALLINT;
}
static CPAccessResult aa64_allint_access(CPUARMState *env,
const ARMCPRegInfo *ri, bool isread)
{
if (!isread && arm_current_el(env) == 1 &&
(arm_hcrx_el2_eff(env) & HCRX_TALLINT)) {
return CP_ACCESS_TRAP_EL2;
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo nmi_reginfo[] = {
{ .name = "ALLINT", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3,
.type = ARM_CP_NO_RAW,
.access = PL1_RW, .accessfn = aa64_allint_access,
.fieldoffset = offsetof(CPUARMState, pstate),
.writefn = aa64_allint_write, .readfn = aa64_allint_read,
.resetfn = arm_cp_reset_ignore },
};
#endif /* TARGET_AARCH64 */
static void define_pmu_regs(ARMCPU *cpu)
@ -9894,6 +9925,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_nv2, cpu)) {
define_arm_cp_regs(cpu, nv2_reginfo);
}
if (cpu_isar_feature(aa64_nmi, cpu)) {
define_arm_cp_regs(cpu, nmi_reginfo);
}
#endif
if (cpu_isar_feature(any_predinv, cpu)) {