ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/arm: Implement ALLINT MSR (immediate) 

Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:32:57 +01:00 committed by Peter Maydell
parent 4833c75611
commit cbf817a2ff
4 changed files with 33 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/arm/tcg/a64.decode
View File

@ -207,6 +207,7 @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
# MRS, MSR (register), SYS, SYSL. These are all essentially the

12
target/arm/tcg/helper-a64.c
View File

@ -66,6 +66,18 @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
update_spsel(env, imm);
}
void HELPER(msr_set_allint_el1)(CPUARMState *env)
{
/* ALLINT update to PSTATE. */
if (arm_hcrx_el2_eff(env) & HCRX_TALLINT) {
raise_exception_ra(env, EXCP_UDEF,
syn_aa64_sysregtrap(0, 1, 0, 4, 1, 0x1f, 0), 2,
GETPC());
}
env->pstate |= PSTATE_ALLINT;
}
static void daif_check(CPUARMState *env, uint32_t op,
uint32_t imm, uintptr_t ra)
{

1
target/arm/tcg/helper-a64.h
View File

@ -22,6 +22,7 @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(msr_i_spsel, void, env, i32)
DEF_HELPER_2(msr_i_daifset, void, env, i32)
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
DEF_HELPER_1(msr_set_allint_el1, void, env)
DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

19
target/arm/tcg/translate-a64.c
View File

@ -2036,6 +2036,25 @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a)
return true;
}
static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
{
if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
return false;
}
if (a->imm == 0) {
clear_pstate_bits(PSTATE_ALLINT);
} else if (s->current_el > 1) {
set_pstate_bits(PSTATE_ALLINT);
} else {
gen_helper_msr_set_allint_el1(tcg_env);
}
/* Exit the cpu loop to re-evaluate pending IRQs. */
s->base.is_jmp = DISAS_UPDATE_EXIT;
return true;
}
static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a)
{
if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) {