mirror of https://github.com/xemu-project/xemu.git
target/riscv: Add J-extension into RISC-V
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -65,6 +65,7 @@
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#define RVS RV('S')
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#define RVU RV('U')
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#define RVH RV('H')
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#define RVJ RV('J')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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@ -291,6 +292,7 @@ struct RISCVCPU {
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bool ext_s;
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bool ext_u;
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bool ext_h;
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bool ext_j;
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bool ext_v;
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bool ext_zba;
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bool ext_zbb;
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