From 53dcea58b8ab150ab034f9c19074c5f74d6ca41e Mon Sep 17 00:00:00 2001 From: Alexey Baturo Date: Mon, 25 Oct 2021 20:36:02 +0300 Subject: [PATCH] target/riscv: Add J-extension into RISC-V Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a33dc30be8..1cfc6a53a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,6 +65,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -291,6 +292,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb;