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target/ppc: Add helpers to check for SMT sibling threads 

Add helpers for TCG code to determine if there are SMT siblings
sharing per-core and per-lpar registers. This simplifies the
callers and makes SMT register topology simpler to modify with
later changes.

Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-24 17:49:52 +10:00
parent feb37fdc82
commit 50d8cfb949
5 changed files with 30 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
target/ppc/cpu.h
View File

@ -1512,6 +1512,17 @@ struct PowerPCCPUClass {
int (*check_attn)(CPUPPCState *env); int (*check_attn)(CPUPPCState *env);
}; };
static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
{
return cs->nr_threads == 1;
}
static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
{
return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) ||
ppc_cpu_core_single_threaded(cs);
}
ObjectClass *ppc_cpu_class_by_name(const char *name); ObjectClass *ppc_cpu_class_by_name(const char *name);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);

2
target/ppc/cpu_init.c
View File

@ -6976,7 +6976,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
pcc->parent_realize(dev, errp); pcc->parent_realize(dev, errp);
if (env_cpu(env)->nr_threads > 1) { if (!ppc_cpu_core_single_threaded(cs)) {
env->flags |= POWERPC_FLAG_SMT; env->flags |= POWERPC_FLAG_SMT;
} }

17
target/ppc/excp_helper.c
View File

@ -3005,18 +3005,11 @@ static void msgsnd_core_tir(CPUPPCState *env, uint32_t target_tir, int irq)
{ {
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
uint32_t nr_threads = cs->nr_threads;
if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/ if (target_tir == 0) {
} ppc_set_irq(cpu, irq, 1);
}
if (target_tir >= nr_threads) {
return;
}
if (nr_threads == 1) {
ppc_set_irq(cpu, irq, 1);
} else { } else {
CPUState *ccs; CPUState *ccs;
@ -3071,7 +3064,7 @@ void helper_book3s_msgsnd(CPUPPCState *env, target_ulong rb)
brdcast = true; brdcast = true;
} }
if (cs->nr_threads == 1 || !brdcast) { if (ppc_cpu_core_single_threaded(cs) || !brdcast) {
ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1); ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1);
return; return;
} }

27
target/ppc/misc_helper.c
View File

@ -48,9 +48,8 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1) { if (ppc_cpu_core_single_threaded(cs)) {
env->spr[sprn] = val; env->spr[sprn] = val;
return; return;
} }
@ -195,7 +194,7 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val)
return; return;
} }
if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
env->spr[SPR_PTCR] = val; env->spr[SPR_PTCR] = val;
tlb_flush(cs); tlb_flush(cs);
} else { } else {
@ -242,16 +241,12 @@ target_ulong helper_load_dpdes(CPUPPCState *env)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
target_ulong dpdes = 0; target_ulong dpdes = 0;
helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { /* DPDES behaves as 1-thread in LPAR-per-thread mode */
nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ if (ppc_cpu_lpar_single_threaded(cs)) {
}
if (nr_threads == 1) {
if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
dpdes = 1; dpdes = 1;
} }
@ -278,21 +273,11 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { /* DPDES behaves as 1-thread in LPAR-per-thread mode */
nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ if (ppc_cpu_lpar_single_threaded(cs)) {
}
if (val & ~(nr_threads - 1)) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
TARGET_FMT_lx"\n", val);
val &= (nr_threads - 1); /* Ignore the invalid bits */
}
if (nr_threads == 1) {
ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
return; return;
} }

20
target/ppc/timebase_helper.c
View File

@ -62,9 +62,8 @@ void helper_store_purr(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_purr(env, val); cpu_ppc_store_purr(env, val);
return; return;
} }
@ -81,9 +80,8 @@ void helper_store_tbl(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_tbl(env, val); cpu_ppc_store_tbl(env, val);
return; return;
} }
@ -98,9 +96,8 @@ void helper_store_tbu(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_tbu(env, val); cpu_ppc_store_tbu(env, val);
return; return;
} }
@ -140,9 +137,8 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_hdecr(env, val); cpu_ppc_store_hdecr(env, val);
return; return;
} }
@ -157,9 +153,8 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_vtb(env, val); cpu_ppc_store_vtb(env, val);
return; return;
} }
@ -174,9 +169,8 @@ void helper_store_tbu40(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
CPUState *ccs; CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { if (ppc_cpu_lpar_single_threaded(cs)) {
cpu_ppc_store_tbu40(env, val); cpu_ppc_store_tbu40(env, val);
return; return;
} }
@ -293,7 +287,7 @@ static void write_tfmr(CPUPPCState *env, target_ulong val)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
if (cs->nr_threads == 1) { if (ppc_cpu_core_single_threaded(cs)) {
env->spr[SPR_TFMR] = val; env->spr[SPR_TFMR] = val;
} else { } else {
CPUState *ccs; CPUState *ccs;