mirror of https://github.com/xemu-project/xemu.git
ppc: Add a core_index to CPUPPCState for SMT vCPUs
The way SMT thread siblings are matched is clunky, using hard-coded logic that checks the PIR SPR. Change that to use a new core_index variable in the CPUPPCState, where all siblings have the same core_index. CPU realize routines have flexibility in setting core/sibling topology. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
parent
25de28220c
commit
feb37fdc82
|
@ -249,6 +249,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
|
|||
pir_spr->default_value = pir;
|
||||
tir_spr->default_value = tir;
|
||||
|
||||
env->core_index = core_hwid;
|
||||
|
||||
/* Set time-base frequency to 512 MHz */
|
||||
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
|
||||
}
|
||||
|
|
|
@ -300,11 +300,13 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
|
|||
g_autofree char *id = NULL;
|
||||
CPUState *cs;
|
||||
PowerPCCPU *cpu;
|
||||
CPUPPCState *env;
|
||||
|
||||
obj = object_new(scc->cpu_type);
|
||||
|
||||
cs = CPU(obj);
|
||||
cpu = POWERPC_CPU(obj);
|
||||
env = &cpu->env;
|
||||
/*
|
||||
* All CPUs start halted. CPU0 is unhalted from the machine level reset code
|
||||
* and the rest are explicitly started up by the guest using an RTAS call.
|
||||
|
@ -315,6 +317,8 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
env->core_index = cc->core_id;
|
||||
|
||||
cpu->node_id = sc->node_id;
|
||||
|
||||
id = g_strdup_printf("thread[%d]", i);
|
||||
|
|
|
@ -1247,6 +1247,9 @@ struct CPUArchState {
|
|||
/* when a memory exception occurs, the access type is stored here */
|
||||
int access_type;
|
||||
|
||||
/* For SMT processors */
|
||||
int core_index;
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* MMU context, only relevant for full system emulation */
|
||||
#if defined(TARGET_PPC64)
|
||||
|
@ -1402,12 +1405,10 @@ struct CPUArchState {
|
|||
uint64_t pmu_base_time;
|
||||
};
|
||||
|
||||
#define _CORE_ID(cs) \
|
||||
(POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1))
|
||||
|
||||
#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
|
||||
CPU_FOREACH(cs_sibling) \
|
||||
if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
|
||||
if (POWERPC_CPU(cs)->env.core_index == \
|
||||
POWERPC_CPU(cs_sibling)->env.core_index)
|
||||
|
||||
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
|
||||
do { \
|
||||
|
|
Loading…
Reference in New Issue