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target/arm: Do not use gen_mte_checkN in trans_STGP 

STGP writes to tag memory, it does not check it.
This happened to work because we wrote tag memory first
so that the check always succeeded.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230901203103.136408-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-01 13:31:03 -07:00 committed by Peter Maydell
parent 4a0244b4b2
commit 44e0ddee8e
1 changed files with 15 additions and 26 deletions
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41
target/arm/tcg/translate-a64.c
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@ -3020,37 +3020,17 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
} }
if (!s->ata) { clean_addr = clean_data_tbi(s, dirty_addr);
/*
* TODO: We could rely on the stores below, at least for
* system mode, if we arrange to add MO_ALIGN_16.
*/
gen_helper_stg_stub(cpu_env, dirty_addr);
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
} else {
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
}
mop = finalize_memop(s, MO_64);
clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << MO_64, mop);
tcg_rt = cpu_reg(s, a->rt); tcg_rt = cpu_reg(s, a->rt);
tcg_rt2 = cpu_reg(s, a->rt2); tcg_rt2 = cpu_reg(s, a->rt2);
/* /*
* STGP is defined as two 8-byte memory operations and one tag operation. * STGP is defined as two 8-byte memory operations, aligned to TAG_GRANULE,
* We implement it as one single 16-byte memory operation for convenience. * and one tag operation. We implement it as one single aligned 16-byte
* Rebuild mop as for STP. * memory operation for convenience. Note that the alignment ensures
* TODO: The atomicity with LSE2 is stronger than required. * MO_ATOM_IFALIGN_PAIR produces 8-byte atomicity for the memory store.
* Need a form of MO_ATOM_WITHIN16_PAIR that never requires
* 16-byte atomicity.
*/ */
mop = MO_128; mop = finalize_memop_atom(s, MO_128 | MO_ALIGN, MO_ATOM_IFALIGN_PAIR);
if (s->align_mem) {
mop |= MO_ALIGN_8;
}
mop = finalize_memop_pair(s, mop);
tmp = tcg_temp_new_i128(); tmp = tcg_temp_new_i128();
if (s->be_data == MO_LE) { if (s->be_data == MO_LE) {
@ -3060,6 +3040,15 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
} }
tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
/* Perform the tag store, if tag access enabled. */
if (s->ata) {
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr);
} else {
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
}
}
op_addr_ldstpair_post(s, a, dirty_addr, offset); op_addr_ldstpair_post(s, a, dirty_addr, offset);
return true; return true;
} }