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hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG 

Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-9-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Francisco Iglesias 2023-08-31 17:57:01 +01:00 committed by Peter Maydell
parent b286d08aa1
commit 4a0244b4b2
2 changed files with 181 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
hw/arm/xlnx-versal.c
View File

@ -27,7 +27,7 @@
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
#define GEM_REVISION 0x40070106
#define VERSAL_NUM_PMC_APB_IRQS 3
#define VERSAL_NUM_PMC_APB_IRQS 18
#define NUM_OSPI_IRQ_LINES 3
static void versal_create_apu_cpus(Versal *s)
@ -341,6 +341,7 @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic)
* - RTC
* - BBRAM
* - PMC SLCR
* - CFRAME regs (input 3 - 17 to the orgate)
*/
object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate",
&s->pmc.apb_irq_orgate, TYPE_OR_IRQ);
@ -573,6 +574,42 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
static void versal_create_cfu(Versal *s, qemu_irq *pic)
{
SysBusDevice *sbd;
DeviceState *dev;
int i;
const struct {
uint64_t reg_base;
uint64_t fdri_base;
} cframe_addr[] = {
{ MM_PMC_CFRAME0_REG, MM_PMC_CFRAME0_FDRI },
{ MM_PMC_CFRAME1_REG, MM_PMC_CFRAME1_FDRI },
{ MM_PMC_CFRAME2_REG, MM_PMC_CFRAME2_FDRI },
{ MM_PMC_CFRAME3_REG, MM_PMC_CFRAME3_FDRI },
{ MM_PMC_CFRAME4_REG, MM_PMC_CFRAME4_FDRI },
{ MM_PMC_CFRAME5_REG, MM_PMC_CFRAME5_FDRI },
{ MM_PMC_CFRAME6_REG, MM_PMC_CFRAME6_FDRI },
{ MM_PMC_CFRAME7_REG, MM_PMC_CFRAME7_FDRI },
{ MM_PMC_CFRAME8_REG, MM_PMC_CFRAME8_FDRI },
{ MM_PMC_CFRAME9_REG, MM_PMC_CFRAME9_FDRI },
{ MM_PMC_CFRAME10_REG, MM_PMC_CFRAME10_FDRI },
{ MM_PMC_CFRAME11_REG, MM_PMC_CFRAME11_FDRI },
{ MM_PMC_CFRAME12_REG, MM_PMC_CFRAME12_FDRI },
{ MM_PMC_CFRAME13_REG, MM_PMC_CFRAME13_FDRI },
{ MM_PMC_CFRAME14_REG, MM_PMC_CFRAME14_FDRI },
};
const struct {
uint32_t blktype0_frames;
uint32_t blktype1_frames;
uint32_t blktype2_frames;
uint32_t blktype3_frames;
uint32_t blktype4_frames;
uint32_t blktype5_frames;
uint32_t blktype6_frames;
} cframe_cfg[] = {
[0] = { 34111, 3528, 12800, 11, 5, 1, 1 },
[1] = { 38498, 3841, 15361, 13, 7, 3, 1 },
[2] = { 38498, 3841, 15361, 13, 7, 3, 1 },
[3] = { 38498, 3841, 15361, 13, 7, 3, 1 },
};
/* CFU FDRO */
object_initialize_child(OBJECT(s), "cfu-fdro", &s->pmc.cfu_fdro,
@ -583,10 +620,84 @@ static void versal_create_cfu(Versal *s, qemu_irq *pic)
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_FDRO,
sysbus_mmio_get_region(sbd, 0));
/* CFRAME REG */
for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
g_autofree char *name = g_strdup_printf("cframe%d", i);
object_initialize_child(OBJECT(s), name, &s->pmc.cframe[i],
TYPE_XLNX_VERSAL_CFRAME_REG);
sbd = SYS_BUS_DEVICE(&s->pmc.cframe[i]);
dev = DEVICE(&s->pmc.cframe[i]);
if (i < ARRAY_SIZE(cframe_cfg)) {
object_property_set_int(OBJECT(dev), "blktype0-frames",
cframe_cfg[i].blktype0_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype1-frames",
cframe_cfg[i].blktype1_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype2-frames",
cframe_cfg[i].blktype2_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype3-frames",
cframe_cfg[i].blktype3_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype4-frames",
cframe_cfg[i].blktype4_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype5-frames",
cframe_cfg[i].blktype5_frames,
&error_abort);
object_property_set_int(OBJECT(dev), "blktype6-frames",
cframe_cfg[i].blktype6_frames,
&error_abort);
}
object_property_set_link(OBJECT(dev), "cfu-fdro",
OBJECT(&s->pmc.cfu_fdro), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(&s->mr_ps, cframe_addr[i].reg_base,
sysbus_mmio_get_region(sbd, 0));
memory_region_add_subregion(&s->mr_ps, cframe_addr[i].fdri_base,
sysbus_mmio_get_region(sbd, 1));
sysbus_connect_irq(sbd, 0,
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate),
3 + i));
}
/* CFRAME BCAST */
object_initialize_child(OBJECT(s), "cframe_bcast", &s->pmc.cframe_bcast,
TYPE_XLNX_VERSAL_CFRAME_BCAST_REG);
sbd = SYS_BUS_DEVICE(&s->pmc.cframe_bcast);
dev = DEVICE(&s->pmc.cframe_bcast);
for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
g_autofree char *propname = g_strdup_printf("cframe%d", i);
object_property_set_link(OBJECT(dev), propname,
OBJECT(&s->pmc.cframe[i]), &error_fatal);
}
sysbus_realize(sbd, &error_fatal);
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_REG,
sysbus_mmio_get_region(sbd, 0));
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFRAME_BCAST_FDRI,
sysbus_mmio_get_region(sbd, 1));
/* CFU APB */
object_initialize_child(OBJECT(s), "cfu-apb", &s->pmc.cfu_apb,
TYPE_XLNX_VERSAL_CFU_APB);
sbd = SYS_BUS_DEVICE(&s->pmc.cfu_apb);
dev = DEVICE(&s->pmc.cfu_apb);
for (i = 0; i < ARRAY_SIZE(s->pmc.cframe); i++) {
g_autofree char *propname = g_strdup_printf("cframe%d", i);
object_property_set_link(OBJECT(dev), propname,
OBJECT(&s->pmc.cframe[i]), &error_fatal);
}
sysbus_realize(sbd, &error_fatal);
memory_region_add_subregion(&s->mr_ps, MM_PMC_CFU_APB,

69
include/hw/arm/xlnx-versal.h
View File

@ -33,6 +33,7 @@
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "hw/misc/xlnx-versal-cframe-reg.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@ -47,6 +48,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
#define XLNX_VERSAL_NR_IRQS 192
#define XLNX_VERSAL_NR_CANFD 2
#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
#define XLNX_VERSAL_NR_CFRAME 15
struct Versal {
/*< private >*/
@ -121,6 +123,8 @@ struct Versal {
XlnxVersalCFUAPB cfu_apb;
XlnxVersalCFUFDRO cfu_fdro;
XlnxVersalCFUSFR cfu_sfr;
XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
XlnxVersalCFrameBcastReg cframe_bcast;
OrIRQState apb_irq_orgate;
} pmc;
@ -256,6 +260,71 @@ struct Versal {
#define MM_PMC_CFU_STREAM_2 0xf1f80000
#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
#define MM_PMC_CFRAME0_REG 0xf12d0000
#define MM_PMC_CFRAME0_REG_SIZE 0x1000
#define MM_PMC_CFRAME0_FDRI 0xf12d1000
#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME1_REG 0xf12d2000
#define MM_PMC_CFRAME1_REG_SIZE 0x1000
#define MM_PMC_CFRAME1_FDRI 0xf12d3000
#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME2_REG 0xf12d4000
#define MM_PMC_CFRAME2_REG_SIZE 0x1000
#define MM_PMC_CFRAME2_FDRI 0xf12d5000
#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME3_REG 0xf12d6000
#define MM_PMC_CFRAME3_REG_SIZE 0x1000
#define MM_PMC_CFRAME3_FDRI 0xf12d7000
#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME4_REG 0xf12d8000
#define MM_PMC_CFRAME4_REG_SIZE 0x1000
#define MM_PMC_CFRAME4_FDRI 0xf12d9000
#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME5_REG 0xf12da000
#define MM_PMC_CFRAME5_REG_SIZE 0x1000
#define MM_PMC_CFRAME5_FDRI 0xf12db000
#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME6_REG 0xf12dc000
#define MM_PMC_CFRAME6_REG_SIZE 0x1000
#define MM_PMC_CFRAME6_FDRI 0xf12dd000
#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME7_REG 0xf12de000
#define MM_PMC_CFRAME7_REG_SIZE 0x1000
#define MM_PMC_CFRAME7_FDRI 0xf12df000
#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME8_REG 0xf12e0000
#define MM_PMC_CFRAME8_REG_SIZE 0x1000
#define MM_PMC_CFRAME8_FDRI 0xf12e1000
#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME9_REG 0xf12e2000
#define MM_PMC_CFRAME9_REG_SIZE 0x1000
#define MM_PMC_CFRAME9_FDRI 0xf12e3000
#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME10_REG 0xf12e4000
#define MM_PMC_CFRAME10_REG_SIZE 0x1000
#define MM_PMC_CFRAME10_FDRI 0xf12e5000
#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME11_REG 0xf12e6000
#define MM_PMC_CFRAME11_REG_SIZE 0x1000
#define MM_PMC_CFRAME11_FDRI 0xf12e7000
#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME12_REG 0xf12e8000
#define MM_PMC_CFRAME12_REG_SIZE 0x1000
#define MM_PMC_CFRAME12_FDRI 0xf12e9000
#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME13_REG 0xf12ea000
#define MM_PMC_CFRAME13_REG_SIZE 0x1000
#define MM_PMC_CFRAME13_FDRI 0xf12eb000
#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME14_REG 0xf12ec000
#define MM_PMC_CFRAME14_REG_SIZE 0x1000
#define MM_PMC_CFRAME14_FDRI 0xf12ed000
#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000