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target/arm: Add Cortex-R52 IMPDEF sysregs 

Add the Cortex-R52 IMPDEF sysregs, by defining them here and
also by enabling the AUXCR feature which defines the ACTLR
and HACTLR registers. As is our usual practice, we make these
simple reads-as-zero stubs for now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-02-06 13:29:21 +00:00
parent fe31d6c72d
commit 282a48eca4
1 changed files with 108 additions and 0 deletions
target/arm/tcg
cpu32.c

108
target/arm/tcg/cpu32.c
View File

@ -800,6 +800,111 @@ static void cortex_r5_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
}
static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
{ .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
{ .name = "IMP_ATCMREGIONR",
.cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_BTCMREGIONR",
.cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_CTCMREGIONR",
.cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_CSCTLR",
.cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_BPCTLR",
.cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_MEMPROTCLR",
.cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_SLAVEPCTLR",
.cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_PERIPHREGIONR",
.cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_FLASHIFREGIONR",
.cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_BUILDOPTR",
.cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_PINOPTR",
.cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_QOSR",
.cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_BUSTIMEOUTR",
.cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_INTMONR",
.cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_ICERR0",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_ICERR1",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_DCERR0",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_DCERR1",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TCMERR0",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TCMERR1",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TCMSYNDR0",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TCMSYNDR1",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_FLASHERR0",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_FLASHERR1",
.cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_CDBGDR0",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_CBDGBR1",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TESTR0",
.cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "IMP_TESTR1",
.cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
{ .name = "IMP_CDBGDCI",
.cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
{ .name = "IMP_CDBGDCT",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
{ .name = "IMP_CDBGICT",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
{ .name = "IMP_CDBGDCD",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
{ .name = "IMP_CDBGICD",
.cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
};
static void cortex_r52_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@ -810,6 +915,7 @@ static void cortex_r52_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = 0x411fd133; /* r1p3 */
cpu->revidr = 0x00000000;
cpu->reset_fpsid = 0x41034023;
@ -840,6 +946,8 @@ static void cortex_r52_initfn(Object *obj)
cpu->pmsav7_dregion = 16;
cpu->pmsav8r_hdregion = 16;
define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
}
static void cortex_r5f_initfn(Object *obj)