mirror of https://github.com/xemu-project/xemu.git
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-10-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -194,6 +194,14 @@ REG32(IDR, 0x2c) /* Interrupt Disable reg */
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REG32(IMR, 0x30) /* Interrupt Mask reg */
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REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
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FIELD(PHYMNTNC, DATA, 0, 16)
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FIELD(PHYMNTNC, REG_ADDR, 18, 5)
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FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
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FIELD(PHYMNTNC, OP, 28, 2)
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FIELD(PHYMNTNC, ST, 30, 2)
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#define MDIO_OP_READ 0x3
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#define MDIO_OP_WRITE 0x2
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REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
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REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
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REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
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@ -342,13 +350,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
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#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
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#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
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#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
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#define GEM_PHYMNTNC_ADDR_SHFT 23
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#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
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#define GEM_PHYMNTNC_REG_SHIFT 18
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/* Marvell PHY definitions */
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#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
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@ -1541,12 +1542,12 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
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/* The interrupts get updated at the end of the function. */
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break;
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case R_PHYMNTNC:
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if (retval & GEM_PHYMNTNC_OP_R) {
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if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
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uint32_t phy_addr, reg_num;
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phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
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phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
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if (phy_addr == s->phy_addr) {
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reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
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reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
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retval &= 0xFFFF0000;
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retval |= gem_phy_read(s, reg_num);
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} else {
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@ -1664,12 +1665,12 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
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s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
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break;
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case R_PHYMNTNC:
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if (val & GEM_PHYMNTNC_OP_W) {
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if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
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uint32_t phy_addr, reg_num;
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phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
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phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
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if (phy_addr == s->phy_addr) {
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reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
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reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
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gem_phy_write(s, reg_num, val);
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}
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}
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