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hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields 

Use the FIELD macro to describe the DESCONF6 register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2023-10-17 21:44:19 +02:00 committed by Peter Maydell
parent 987e806017
commit ce077875da
1 changed files with 2 additions and 2 deletions
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4
hw/net/cadence_gem.c
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@ -283,7 +283,7 @@ REG32(DESCONF3, 0x288)
REG32(DESCONF4, 0x28c)
REG32(DESCONF5, 0x290)
REG32(DESCONF6, 0x294)
#define GEM_DESCONF6_64B_MASK (1U << 23)
FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
REG32(DESCONF7, 0x298)
REG32(INT_Q1_STATUS, 0x400)
@ -1463,7 +1463,7 @@ static void gem_reset(DeviceState *d)
s->regs[R_DESCONF] = 0x02D00111;
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
s->regs[R_DESCONF5] = 0x002f2045;
s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
s->regs[R_INT_Q1_MASK] = 0x00000CE6;
s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;