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* Assorted small ppc fixes 

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Merge tag 'pull-ppc-for-9.2-2-20241127' of https://gitlab.com/npiggin/qemu into staging

* Assorted small ppc fixes

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# gpg: Signature made Tue 26 Nov 2024 16:57:41 GMT
# gpg:                using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0  A795 67B3 0276 A862 1CAE

* tag 'pull-ppc-for-9.2-2-20241127' of https://gitlab.com/npiggin/qemu:
  hw/ppc/pegasos2: Fix IRQ routing from pci.0
  ppc/spapr: fix drc index mismatch for partially enabled vcpus
  ppc/pnv: Add xscom- prefix to pervasive-control region name
  target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket
  ppc/pnv: Fix direct controls quiesce
  target/ppc: Fix non-maskable interrupt while halted

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-11-26 20:16:26 +00:00
parent 7cbea81618 0805136a44
commit 10bfa161fb
8 changed files with 55 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/pci-host/mv64361.c
View File

@ -95,6 +95,7 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
&s->mem, &s->io, 0, 4, TYPE_PCI_BUS);
g_free(name);
pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE);
qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
}
static Property mv64361_pcihost_props[] = {

30
hw/ppc/pegasos2.c
View File

@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "hw/pci/pci_host.h"
#include "hw/irq.h"
#include "hw/or-irq.h"
#include "hw/pci-host/mv64361.h"
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
@ -73,8 +74,11 @@ OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
struct Pegasos2MachineState {
MachineState parent_obj;
PowerPCCPU *cpu;
DeviceState *mv;
IRQState pci_irqs[PCI_NUM_PINS];
OrIRQState orirq[PCI_NUM_PINS];
qemu_irq mv_pirq[PCI_NUM_PINS];
qemu_irq via_pirq[PCI_NUM_PINS];
Vof *vof;
@ -177,7 +181,6 @@ static void pegasos2_init(MachineState *machine)
pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);
}
pci_bus = mv64361_get_pci_bus(pm->mv, 1);
pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS);
/* VIA VT8231 South Bridge (multifunction PCI device) */
via = OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), TYPE_VT8231_ISA));
@ -209,6 +212,31 @@ static void pegasos2_init(MachineState *machine)
/* other PC hardware */
pci_vga_init(pci_bus);
/* PCI interrupt routing: lines from pci.0 and pci.1 are ORed */
for (int h = 0; h < 2; h++) {
DeviceState *pd;
g_autofree const char *pn = g_strdup_printf("pcihost%d", h);
pd = DEVICE(object_resolve_path_component(OBJECT(pm->mv), pn));
assert(pd);
for (i = 0; i < PCI_NUM_PINS; i++) {
OrIRQState *ori = &pm->orirq[i];
if (h == 0) {
g_autofree const char *n = g_strdup_printf("pci-orirq[%d]", i);
object_initialize_child_with_props(OBJECT(pm), n,
ori, sizeof(*ori),
TYPE_OR_IRQ, &error_fatal,
"num-lines", "2", NULL);
qdev_realize(DEVICE(ori), NULL, &error_fatal);
qemu_init_irq(&pm->pci_irqs[i], pegasos2_pci_irq, pm, i);
qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]);
}
qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h));
}
}
if (machine->kernel_filename) {
sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
&pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,

11
hw/ppc/pnv_core.c
View File

@ -217,8 +217,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
case PNV10_XSCOM_EC_CORE_RAS_STATUS:
for (i = 0; i < nr_threads; i++) {
PowerPCCPU *cpu = pc->threads[i];
CPUState *cs = CPU(cpu);
if (cs->stopped) {
CPUPPCState *env = &cpu->env;
if (env->quiesced) {
val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i);
}
}
@ -244,20 +244,25 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
for (i = 0; i < nr_threads; i++) {
PowerPCCPU *cpu = pc->threads[i];
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
if (val & PPC_BIT(7 + 8 * i)) { /* stop */
val &= ~PPC_BIT(7 + 8 * i);
cpu_pause(cs);
env->quiesced = true;
}
if (val & PPC_BIT(6 + 8 * i)) { /* start */
val &= ~PPC_BIT(6 + 8 * i);
env->quiesced = false;
cpu_resume(cs);
}
if (val & PPC_BIT(4 + 8 * i)) { /* sreset */
val &= ~PPC_BIT(4 + 8 * i);
env->quiesced = false;
pnv_cpu_do_nmi_resume(cs);
}
if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */
env->quiesced = false;
/*
* Hardware has very particular cases for where clear maint
* must be used and where start must be used to resume a
@ -317,6 +322,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
pir_spr->default_value = pir;
tir_spr->default_value = tir;
env->chip_index = pc->chip->chip_id;
if (pc->big_core) {
/* 2 "small cores" get the same core index for SMT operations */
env->core_index = core_hwid >> 1;

2
hw/ppc/pnv_nest_pervasive.c
View File

@ -177,7 +177,7 @@ static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs_mr,
OBJECT(nest_pervasive),
&pnv_nest_pervasive_control_xscom_ops,
nest_pervasive, "pervasive-control",
nest_pervasive, "xscom-pervasive-control",
PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE);
}

2
hw/ppc/spapr.c
View File

@ -701,7 +701,7 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
int i;
drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, env->core_index);
if (drc) {
drc_index = spapr_drc_index(drc);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));

1
hw/ppc/spapr_cpu_core.c
View File

@ -313,6 +313,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
return NULL;
}
env->chip_index = sc->node_id;
env->core_index = cc->core_id;
cpu->node_id = sc->node_id;

8
target/ppc/cpu.h
View File

@ -1253,6 +1253,7 @@ struct CPUArchState {
/* For SMT processors */
bool has_smt_siblings;
int core_index;
int chip_index;
#if !defined(CONFIG_USER_ONLY)
/* MMU context, only relevant for full system emulation */
@ -1355,6 +1356,7 @@ struct CPUArchState {
* special way (such as routing some resume causes to 0x100, i.e. sreset).
*/
bool resume_as_sreset;
bool quiesced;
#endif
/* These resources are used only in TCG */
@ -1411,8 +1413,10 @@ struct CPUArchState {
#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
CPU_FOREACH(cs_sibling) \
if (POWERPC_CPU(cs)->env.core_index == \
POWERPC_CPU(cs_sibling)->env.core_index)
if ((POWERPC_CPU(cs)->env.chip_index == \
POWERPC_CPU(cs_sibling)->env.chip_index) && \
(POWERPC_CPU(cs)->env.core_index == \
POWERPC_CPU(cs_sibling)->env.core_index))
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
do { \

7
target/ppc/excp_helper.c
View File

@ -2495,10 +2495,16 @@ static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
}
}
/*
* system reset is not delivered via normal irq method, so have to set
* halted = 0 to resume CPU running if it was halted. Possibly we should
* move it over to using PPC_INTERRUPT_RESET rather than async_run_on_cpu.
*/
void ppc_cpu_do_system_reset(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
cs->halted = 0;
powerpc_excp(cpu, POWERPC_EXCP_RESET);
}
@ -2520,6 +2526,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
/* Anything for nested required here? MSR[HV] bit? */
cs->halted = 0;
powerpc_set_excp_state(cpu, vector, msr);
}