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target/arm: Add feature detection for FEAT_Pauth2 and extensions 

Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5
to distinguish the other architectural algorithm qarma3.

Add ARMPauthFeature and isar_feature_pauth_feature to cover the
other pauth conditions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-4-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-3-aaron@os.amperecomputing.com>
[rth: Add ARMPauthFeature and eliminate most other predicates]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Aaron Lindsay 2023-08-29 16:23:26 -07:00 committed by Peter Maydell
parent a969fe9755
commit 0274bd7be7
2 changed files with 40 additions and 9 deletions
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47
target/arm/cpu.h
View File

@ -3804,28 +3804,59 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
}
/*
* These are the values from APA/API/APA3.
* In general these must be compared '>=', per the normal Arm ARM
* treatment of fields in ID registers.
*/
typedef enum {
PauthFeat_None = 0,
PauthFeat_1 = 1,
PauthFeat_EPAC = 2,
PauthFeat_2 = 3,
PauthFeat_FPAC = 4,
PauthFeat_FPACCOMBINED = 5,
} ARMPauthFeature;
static inline ARMPauthFeature
isar_feature_pauth_feature(const ARMISARegisters *id)
{
/*
* Architecturally, only one of {APA,API,APA3} may be active (non-zero)
* and the other two must be zero. Thus we may avoid conditionals.
*/
return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
}
static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
{
/*
* Return true if any form of pauth is enabled, as this
* predicate controls migration of the 128-bit keys.
*/
return (id->id_aa64isar1 &
(FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
return isar_feature_pauth_feature(id) != PauthFeat_None;
}
static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
{
/*
* Return true if pauth is enabled with the architected QARMA algorithm.
* QEMU will always set APA+GPA to the same value.
* Return true if pauth is enabled with the architected QARMA5 algorithm.
* QEMU will always enable or disable both APA and GPA.
*/
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
}
static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
{
/*
* Return true if pauth is enabled with the architected QARMA3 algorithm.
* QEMU will always enable or disable both APA3 and GPA3.
*/
return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
}
static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;

2
target/arm/tcg/pauth_helper.c
View File

@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier,
static uint64_t pauth_computepac(CPUARMState *env, uint64_t data,
uint64_t modifier, ARMPACKey key)
{
if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) {
if (cpu_isar_feature(aa64_pauth_qarma5, env_archcpu(env))) {
return pauth_computepac_architected(data, modifier, key);
} else {
return pauth_computepac_impdef(data, modifier, key);