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target/arm: Add feature detection for FEAT_Pauth2 and extensions
Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5 to distinguish the other architectural algorithm qarma3. Add ARMPauthFeature and isar_feature_pauth_feature to cover the other pauth conditions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230829232335.965414-4-richard.henderson@linaro.org Message-Id: <20230609172324.982888-3-aaron@os.amperecomputing.com> [rth: Add ARMPauthFeature and eliminate most other predicates] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3804,28 +3804,59 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
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}
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/*
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* These are the values from APA/API/APA3.
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* In general these must be compared '>=', per the normal Arm ARM
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* treatment of fields in ID registers.
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*/
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typedef enum {
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PauthFeat_None = 0,
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PauthFeat_1 = 1,
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PauthFeat_EPAC = 2,
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PauthFeat_2 = 3,
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PauthFeat_FPAC = 4,
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PauthFeat_FPACCOMBINED = 5,
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} ARMPauthFeature;
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static inline ARMPauthFeature
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isar_feature_pauth_feature(const ARMISARegisters *id)
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{
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/*
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* Architecturally, only one of {APA,API,APA3} may be active (non-zero)
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* and the other two must be zero. Thus we may avoid conditionals.
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*/
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return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
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FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
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FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
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}
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static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
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{
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/*
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* Return true if any form of pauth is enabled, as this
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* predicate controls migration of the 128-bit keys.
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*/
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return (id->id_aa64isar1 &
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(FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
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FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
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return isar_feature_pauth_feature(id) != PauthFeat_None;
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}
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static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
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{
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/*
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* Return true if pauth is enabled with the architected QARMA algorithm.
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* QEMU will always set APA+GPA to the same value.
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* Return true if pauth is enabled with the architected QARMA5 algorithm.
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* QEMU will always enable or disable both APA and GPA.
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*/
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
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}
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static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
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{
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/*
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* Return true if pauth is enabled with the architected QARMA3 algorithm.
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* QEMU will always enable or disable both APA3 and GPA3.
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*/
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
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}
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static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
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@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier,
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static uint64_t pauth_computepac(CPUARMState *env, uint64_t data,
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uint64_t modifier, ARMPACKey key)
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{
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if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) {
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if (cpu_isar_feature(aa64_pauth_qarma5, env_archcpu(env))) {
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return pauth_computepac_architected(data, modifier, key);
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} else {
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return pauth_computepac_impdef(data, modifier, key);
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