mirror of https://github.com/xemu-project/xemu.git
target/arm: Add ID_AA64ISAR2_EL1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230829232335.965414-3-richard.henderson@linaro.org [PMM: drop the HVF part of the patch and just comment that we need to do something when the register appears in that API] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1033,6 +1033,7 @@ struct ArchCPU {
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uint32_t dbgdevid1;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64isar2;
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uint64_t id_aa64pfr0;
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uint64_t id_aa64pfr1;
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uint64_t id_aa64mmfr0;
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@ -8435,11 +8435,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid3,
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.resetvalue = cpu->isar.id_aa64isar1 },
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{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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{ .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa64_tid3,
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.resetvalue = 0 },
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.resetvalue = cpu->isar.id_aa64isar2 },
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{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
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.access = PL1_R, .type = ARM_CP_CONST,
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@ -847,6 +847,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
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{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
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{ HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
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/* Add ID_AA64ISAR2_EL1 here when HVF supports it */
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{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
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{ HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
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{ HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
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@ -304,6 +304,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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ARM64_SYS_REG(3, 0, 0, 6, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
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ARM64_SYS_REG(3, 0, 0, 6, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
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ARM64_SYS_REG(3, 0, 0, 6, 2));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
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ARM64_SYS_REG(3, 0, 0, 7, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
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