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xemu/target/mips/tcg/loong-ext.decode

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target/mips: Convert Loongson DDIV.G opcodes to decodetree Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20241026175349.84523-5-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2021-01-12 21:28:57 +00:00
# Loongson 64-bit Extension instructions
#
# Copyright (C) 2021 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference:
# STLS2F01 User Manual
# Appendix A: new integer instructions
# (Document Number: UM0447)
#
&muldiv rs rt rd !extern
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
target/mips: Convert Loongson DIV.G opcodes to decodetree DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbose by providing both variants at once. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20241026175349.84523-6-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2021-01-12 19:08:32 +00:00
DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
target/mips: Convert Loongson DDIV.G opcodes to decodetree Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20241026175349.84523-5-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2021-01-12 21:28:57 +00:00
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd