ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/mips: Convert Loongson DDIV.G opcodes to decodetree 

Introduce decode_loongson() to decode all Loongson vendor
specific opcodes. Start converting a single opcode: DDIV.G
(divide 64-bit signed integers).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-5-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-12 22:28:57 +01:00 committed by Philippe Mathieu-Daudé
parent 869f428fa7
commit 2cb2674698
6 changed files with 126 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
target/mips/tcg/godson2.decode Normal file
View File

@ -0,0 +1,16 @@
# Godson2 64-bit Integer instructions
#
# Copyright (C) 2021 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference:
# Godson-2E Software Manual
# (Document Number: godson2e-user-manual-V0.6)
#
&muldiv rs rt rd
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd

17
target/mips/tcg/loong-ext.decode Normal file
View File

@ -0,0 +1,17 @@
# Loongson 64-bit Extension instructions
#
# Copyright (C) 2021 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference:
# STLS2F01 User Manual
# Appendix A: new integer instructions
# (Document Number: UM0447)
#
&muldiv rs rt rd !extern
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd

86
target/mips/tcg/loong_translate.c Normal file
View File

@ -0,0 +1,86 @@
/*
* MIPS Loongson 64-bit translation routines
*
* Copyright (c) 2004-2005 Jocelyn Mayer
* Copyright (c) 2006 Marius Groeger (FPU operations)
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2011 Richard Henderson <rth@twiddle.net>
* Copyright (c) 2021 Philippe Mathieu-Daudé
*
* This code is licensed under the GNU GPLv2 and later.
*/
#include "qemu/osdep.h"
#include "translate.h"
/* Include the auto-generated decoder. */
#include "decode-godson2.c.inc"
#include "decode-loong-ext.c.inc"
/*
* Word or double-word Fixed-point instructions.
* ---------------------------------------------
*
* Fixed-point multiplies and divisions write only
* one result into general-purpose registers.
*/
static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
{
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
if (TARGET_LONG_BITS != 64) {
return false;
}
check_mips_64(s);
if (rd == 0) {
/* Treat as NOP. */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
l1 = gen_new_label();
l2 = gen_new_label();
l3 = gen_new_label();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
gen_set_label(l3);
return true;
}
static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
{
return gen_lext_DIV_G(s, a->rd, a->rs, a->rt);
}
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
{
if (!decode_64bit_enabled(ctx)) {
return false;
}
if ((ctx->insn_flags & INSN_LOONGSON2E) && decode_godson2(ctx, ctx->opcode)) {
return true;
}
if ((ctx->insn_flags & ASE_LEXT) && decode_loong_ext(ctx, ctx->opcode)) {
return true;
}
return false;
}

3
target/mips/tcg/meson.build
View File

@ -5,6 +5,8 @@ gen = [
decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
decodetree.process('lcsr.decode', extra_args: '--decode=decode_ase_lcsr'),
decodetree.process('godson2.decode', extra_args: ['--static-decode=decode_godson2']),
decodetree.process('loong-ext.decode', extra_args: ['--static-decode=decode_loong_ext']),
]
mips_ss.add(gen)
@ -28,6 +30,7 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
'octeon_translate.c',
'lcsr_translate.c',
'loong_translate.c',
), if_false: files(
'mxu_translate.c',
))

26
target/mips/tcg/translate.c
View File

@ -333,7 +333,6 @@ enum {
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
@ -375,7 +374,6 @@ enum {
OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
@ -3698,25 +3696,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
case OPC_DDIV_G_2E:
case OPC_DDIV_G_2F:
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGLabel *l3 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
gen_set_label(l3);
}
break;
case OPC_DDIVU_G_2E:
case OPC_DDIVU_G_2F:
{
@ -13654,7 +13633,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
case OPC_DDIV_G_2F:
case OPC_DDIVU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
@ -14061,7 +14039,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
case OPC_DDIV_G_2E:
case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
@ -15262,6 +15239,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return;
}
if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) {
return;
}
#if defined(TARGET_MIPS64)
if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) {
return;

1
target/mips/tcg/translate.h
View File

@ -223,6 +223,7 @@ bool decode_64bit_enabled(DisasContext *ctx);
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ase_lcsr(DisasContext *ctx, uint32_t insn);
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);