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xemu/target/ppc/insn32.decode

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target/ppc: Add infrastructure for prefixed insns Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:17 +00:00
#
# Power ISA decode for 32-bit insns (opcode space 0)
#
# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-5-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:18 +00:00
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent. If deemed necessary, a future patch can adapt this behavior based on the specific CPU model. [1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:28 +00:00
&D_bf bf l:bool ra imm
@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
target/ppc: Move LQ and STQ to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-6-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:55 +00:00
%dq_si 4:s12 !function=times_16
%dq_rtp 22:4 !function=times_2
@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
target/ppc: Move D/DS/X-form integer loads to decodetree These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:20 +00:00
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
target/ppc: Move LQ and STQ to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-6-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:55 +00:00
%ds_rtp 22:4 !function=times_2
@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
target/ppc: Move addpcis to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:27 +00:00
&DX rt d
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
target/ppc: Implement vcfuged instruction Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:26 +00:00
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
target/ppc: Move D/DS/X-form integer loads to decodetree These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:20 +00:00
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-11-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:24 +00:00
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent. If deemed necessary, a future patch can adapt this behavior based on the specific CPU model. [1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:28 +00:00
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
target/ppc: Move D/DS/X-form integer loads to decodetree These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:20 +00:00
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
LBZU 100011 ..... ..... ................ @D
LBZX 011111 ..... ..... ..... 0001010111 - @X
LBZUX 011111 ..... ..... ..... 0001110111 - @X
LHZ 101000 ..... ..... ................ @D
LHZU 101001 ..... ..... ................ @D
LHZX 011111 ..... ..... ..... 0100010111 - @X
LHZUX 011111 ..... ..... ..... 0100110111 - @X
LHA 101010 ..... ..... ................ @D
LHAU 101011 ..... ..... ................ @D
LHAX 011111 ..... ..... ..... 0101010111 - @X
LHAXU 011111 ..... ..... ..... 0101110111 - @X
LWZ 100000 ..... ..... ................ @D
LWZU 100001 ..... ..... ................ @D
LWZX 011111 ..... ..... ..... 0000010111 - @X
LWZUX 011111 ..... ..... ..... 0000110111 - @X
LWA 111010 ..... ..... ..............10 @DS
LWAX 011111 ..... ..... ..... 0101010101 - @X
LWAUX 011111 ..... ..... ..... 0101110101 - @X
LD 111010 ..... ..... ..............00 @DS
LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
target/ppc: Move LQ and STQ to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-6-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:55 +00:00
LQ 111000 ..... ..... ............ ---- @DQ_rtp
target/ppc: Move D/DS/X-form integer stores to decodetree These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:22 +00:00
### Fixed-Point Store Instructions
STB 100110 ..... ..... ................ @D
STBU 100111 ..... ..... ................ @D
STBX 011111 ..... ..... ..... 0011010111 - @X
STBUX 011111 ..... ..... ..... 0011110111 - @X
STH 101100 ..... ..... ................ @D
STHU 101101 ..... ..... ................ @D
STHX 011111 ..... ..... ..... 0110010111 - @X
STHUX 011111 ..... ..... ..... 0110110111 - @X
STW 100100 ..... ..... ................ @D
STWU 100101 ..... ..... ................ @D
STWX 011111 ..... ..... ..... 0010010111 - @X
STWUX 011111 ..... ..... ..... 0010110111 - @X
STD 111110 ..... ..... ..............00 @DS
STDU 111110 ..... ..... ..............01 @DS
STDX 011111 ..... ..... ..... 0010010101 - @X
STDUX 011111 ..... ..... ..... 0010110101 - @X
target/ppc: Move LQ and STQ to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-6-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:55 +00:00
STQ 111110 ..... ..... ..............10 @DS_rtp
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent. If deemed necessary, a future patch can adapt this behavior based on the specific CPU model. [1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:28 +00:00
### Fixed-Point Compare Instructions
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
CMPI 001011 ... - . ..... ................ @D_bfs
CMPLI 001010 ... - . ..... ................ @D_bfu
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-5-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:18 +00:00
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-11-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:24 +00:00
target/ppc: Move addpcis to decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:27 +00:00
ADDPCIS 010011 ..... ..... .......... 00010 . @DX
target/ppc: Implement cfuged instruction Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:25 +00:00
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
target/ppc: Implement cntlzdm Implement the following PowerISA v3.1 instruction: cntlzdm: Count Leading Zeros Doubleword Under Bit Mask Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-8-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:57 +00:00
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
target/ppc: Implement cnttzdm Implement the following PowerISA v3.1 instruction: cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-9-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:58 +00:00
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
target/ppc: Implement pdepd instruction Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-10-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:59 +00:00
PDEPD 011111 ..... ..... ..... 0010011100 - @X
target/ppc: Implement cfuged instruction Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:25 +00:00
target/ppc: Move load and store floating point instructions to decodetree Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux) and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx, stfdux) from legacy system to decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 20:23:53 +00:00
### Float-Point Load Instructions
LFS 110000 ..... ..... ................ @D
LFSU 110001 ..... ..... ................ @D
LFSX 011111 ..... ..... ..... 1000010111 - @X
LFSUX 011111 ..... ..... ..... 1000110111 - @X
LFD 110010 ..... ..... ................ @D
LFDU 110011 ..... ..... ................ @D
LFDX 011111 ..... ..... ..... 1001010111 - @X
LFDUX 011111 ..... ..... ..... 1001110111 - @X
### Float-Point Store Instructions
STFS 110100 ..... ...... ............... @D
STFSU 110101 ..... ...... ............... @D
STFSX 011111 ..... ...... .... 1010010111 - @X
STFSUX 011111 ..... ...... .... 1010110111 - @X
STFD 110110 ..... ...... ............... @D
STFDU 110111 ..... ...... ............... @D
STFDX 011111 ..... ...... .... 1011010111 - @X
STFDUX 011111 ..... ...... .... 1011110111 - @X
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-11-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:24 +00:00
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
target/ppc: Implement vcfuged instruction Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-01 19:35:26 +00:00
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX