ShuriZma
/
visualboyadvance-m
mirror of https://github.com/visualboyadvance-m/visualboyadvance-m.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #88 from negativeExponent/backport 

Backport
This commit is contained in:
hizzlekizzle 2020-08-11 09:35:33 -05:00 committed by GitHub
parent 29dffc0120 97637f16d6
commit 364a182968
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 31 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -16,6 +16,7 @@ vcpkg/*
*.so *.so
*.dll *.dll
*.exe *.exe
.vscode
# vim swap files # vim swap files
*.sw? *.sw?

11
src/gba/GBA-arm.cpp
View File

@ -1251,7 +1251,7 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES)
clockTicks += 3; \ clockTicks += 3; \
if (busPrefetchCount == 0) \ if (busPrefetchCount == 0) \
busPrefetchCount = ((busPrefetchCount + 1) << clockTicks) - 1; \ busPrefetchCount = ((busPrefetchCount + 1) << clockTicks) - 1; \
clockTicks += 1 + codeTicksAccess32(armNextPC); clockTicks += CYCLES + 1 + codeTicksAccess32(armNextPC);
#define OP_MUL \ #define OP_MUL \
reg[dest].I = reg[mult].I * rs; reg[dest].I = reg[mult].I * rs;
@ -2581,8 +2581,7 @@ static INSN_REGPARM void armA00(uint32_t opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2595,8 +2594,7 @@ static INSN_REGPARM void armB00(uint32_t opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2612,8 +2610,7 @@ static INSN_REGPARM void armE01(uint32_t opcode)
// SWI <comment> // SWI <comment>
static INSN_REGPARM void armF00(uint32_t opcode) static INSN_REGPARM void armF00(uint32_t opcode)
{ {
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
CPUSoftwareInterrupt(opcode & 0x00FFFFFF); CPUSoftwareInterrupt(opcode & 0x00FFFFFF);
} }

16
src/gba/GBA-thumb.cpp
View File

@ -1146,9 +1146,9 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode)
reg[dest].I = reg[(opcode >> 3) & 7].I * rm; reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
if (((int32_t)rm) < 0) if (((int32_t)rm) < 0)
rm = ~rm; rm = ~rm;
if ((rm & 0xFFFFFF00) == 0) if ((rm & 0xFFFFFF00) == 0) {
clockTicks += 0; // clockTicks += 0;
else if ((rm & 0xFFFF0000) == 0) } else if ((rm & 0xFFFF0000) == 0)
clockTicks += 1; clockTicks += 1;
else if ((rm & 0xFF000000) == 0) else if ((rm & 0xFF000000) == 0)
clockTicks += 2; clockTicks += 2;
@ -1594,7 +1594,7 @@ static INSN_REGPARM void thumbBC(uint32_t opcode)
POP_REG(64, 6); POP_REG(64, 6);
POP_REG(128, 7); POP_REG(128, 7);
reg[13].I = temp; reg[13].I = temp;
clockTicks = 2 + codeTicksAccess16(armNextPC); clockTicks += 2 + codeTicksAccess16(armNextPC);
} }
// POP {Rlist, PC} // POP {Rlist, PC}
@ -1625,7 +1625,7 @@ static INSN_REGPARM void thumbBD(uint32_t opcode)
reg[13].I = temp; reg[13].I = temp;
THUMB_PREFETCH; THUMB_PREFETCH;
busPrefetchCount = 0; busPrefetchCount = 0;
clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC); clockTicks += 3 + (codeTicksAccess16(armNextPC) * 2);
} }
// Load/store multiple //////////////////////////////////////////////////// // Load/store multiple ////////////////////////////////////////////////////
@ -1673,7 +1673,7 @@ static INSN_REGPARM void thumbC0(uint32_t opcode)
THUMB_STM_REG(32, 5, regist); THUMB_STM_REG(32, 5, regist);
THUMB_STM_REG(64, 6, regist); THUMB_STM_REG(64, 6, regist);
THUMB_STM_REG(128, 7, regist); THUMB_STM_REG(128, 7, regist);
clockTicks = 1 + codeTicksAccess16(armNextPC); clockTicks += 1 + codeTicksAccess16(armNextPC);
} }
// LDM R0~R7!, {Rlist} // LDM R0~R7!, {Rlist}
@ -1694,7 +1694,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
THUMB_LDM_REG(32, 5); THUMB_LDM_REG(32, 5);
THUMB_LDM_REG(64, 6); THUMB_LDM_REG(64, 6);
THUMB_LDM_REG(128, 7); THUMB_LDM_REG(128, 7);
clockTicks = 2 + codeTicksAccess16(armNextPC); clockTicks += 2 + codeTicksAccess16(armNextPC);
if (!(opcode & (1 << regist))) if (!(opcode & (1 << regist)))
reg[regist].I = temp; reg[regist].I = temp;
} }
@ -1703,7 +1703,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
#define THUMB_CONDITIONAL_BRANCH(COND) \ #define THUMB_CONDITIONAL_BRANCH(COND) \
UPDATE_OLDREG; \ UPDATE_OLDREG; \
clockTicks = codeTicksAccessSeq16(armNextPC) + 1; \ clockTicks = codeTicksAccessSeq16(armNextPC) + 1; \
if (COND) { \ if ((bool)COND) { \
uint32_t offset = (uint32_t)((int8_t)(opcode & 0xFF)) << 1; \ uint32_t offset = (uint32_t)((int8_t)(opcode & 0xFF)) << 1; \
reg[15].I += offset; \ reg[15].I += offset; \
armNextPC = reg[15].I; \ armNextPC = reg[15].I; \

35
src/gba/GBAinline.h
View File

@ -103,16 +103,17 @@ static inline uint32_t CPUReadMemory(uint32_t address)
case 5: case 5:
value = READ32LE(((uint32_t*)&paletteRAM[address & 0x3fC])); value = READ32LE(((uint32_t*)&paletteRAM[address & 0x3fC]));
break; break;
case 6: case 6: {
address = (address & 0x1fffc); unsigned addr = (address & 0x1fffc);
if (((DISPCNT & 7) > 2) && ((address & 0x1C000) == 0x18000)) { if (((DISPCNT & 7) > 2) && ((addr & 0x1C000) == 0x18000)) {
value = 0; value = 0;
break; break;
} }
if ((address & 0x18000) == 0x18000) if ((addr & 0x18000) == 0x18000)
address &= 0x17fff; addr &= 0x17fff;
value = READ32LE(((uint32_t*)&vram[address])); value = READ32LE(((uint32_t*)&vram[addr]));
break; break;
}
case 7: case 7:
value = READ32LE(((uint32_t*)&oam[address & 0x3FC])); value = READ32LE(((uint32_t*)&oam[address & 0x3FC]));
break; break;
@ -253,16 +254,17 @@ static inline uint32_t CPUReadHalfWord(uint32_t address)
case 5: case 5:
value = READ16LE(((uint16_t*)&paletteRAM[address & 0x3fe])); value = READ16LE(((uint16_t*)&paletteRAM[address & 0x3fe]));
break; break;
case 6: case 6: {
address = (address & 0x1fffe); unsigned addr = (address & 0x1fffe);
if (((DISPCNT & 7) > 2) && ((address & 0x1C000) == 0x18000)) { if (((DISPCNT & 7) > 2) && ((addr & 0x1C000) == 0x18000)) {
value = 0; value = 0;
break; break;
} }
if ((address & 0x18000) == 0x18000) if ((addr & 0x18000) == 0x18000)
address &= 0x17fff; addr &= 0x17fff;
value = READ16LE(((uint16_t*)&vram[address])); value = READ16LE(((uint16_t*)&vram[addr]));
break; break;
}
case 7: case 7:
value = READ16LE(((uint16_t*)&oam[address & 0x3fe])); value = READ16LE(((uint16_t*)&oam[address & 0x3fe]));
break; break;
@ -293,11 +295,10 @@ static inline uint32_t CPUReadHalfWord(uint32_t address)
if (cpuDmaHack) { if (cpuDmaHack) {
value = cpuDmaLast & 0xFFFF; value = cpuDmaLast & 0xFFFF;
} else { } else {
if (armState) { int param = reg[15].I;
value = CPUReadHalfWordQuick(reg[15].I + (address & 2)); if (armState)
} else { param += (address & 2);
value = CPUReadHalfWordQuick(reg[15].I); value = CPUReadHalfWordQuick(param);
}
} }
#ifdef GBA_LOGGING #ifdef GBA_LOGGING
if (systemVerbose & VERBOSE_ILLEGAL_READ) { if (systemVerbose & VERBOSE_ILLEGAL_READ) {