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Applied fixes to NormMatts r1150 fixes - V-Rally 3 working again 

Re-added nasm.props to vs2008 build folder + changes to nasm.rules for spaces in paths.

git-svn-id: https://svn.code.sf.net/p/vbam/code/branches/bgk-link@1161 a31d4220-a93d-0410-bf67-fe4944624d44
This commit is contained in:
squall-leonhart 2013-02-04 06:15:53 +00:00
parent bd0de11177
commit 0d4be24a83
3 changed files with 68 additions and 28 deletions
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26
project/vc2008_mfc/nasm.props Normal file
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@ -0,0 +1,26 @@
<?xml version="1.0" encoding="utf-8"?>
<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<PropertyGroup
Condition="'$(NASMBeforeTargets)' == '' and '$(NASMAfterTargets)' == '' and '$(ConfigurationType)' != 'Makefile'">
<NASMBeforeTargets>Midl</NASMBeforeTargets>
<NASMAfterTargets>CustomBuild</NASMAfterTargets>
</PropertyGroup>
<PropertyGroup>
<NASMDependsOn
Condition="'$(ConfigurationType)' != 'Makefile'">_SelectedFiles;$(NASMDependsOn)</NASMDependsOn>
</PropertyGroup>
<ItemDefinitionGroup>
<NASM>
<TreatWarningsAsErrors>False</TreatWarningsAsErrors>
<DisableOrphanLabelsWarning>False</DisableOrphanLabelsWarning>
<GenerateDebugInfo>False</GenerateDebugInfo>
<ObjectFileName>$(IntDir)%(Filename).obj</ObjectFileName>
<Optimization>0</Optimization>
<ObjectFileFormat>8</ObjectFileFormat>
<ErrorReportingFormat>1</ErrorReportingFormat>
<CommandLineTemplate>"$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]</CommandLineTemplate>
<Outputs>%(ObjectFileName)</Outputs>
<ExecutionDescription>Assembling...</ExecutionDescription>
</NASM>
</ItemDefinitionGroup>
</Project>

5
project/vc2008_mfc/nasm.rules
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@ -7,11 +7,10 @@
<CustomBuildRule <CustomBuildRule
Name="NASM" Name="NASM"
DisplayName="Netwide Assembler" DisplayName="Netwide Assembler"
CommandLine="$(SolutionDir)..\..\..\dependencies\nasm.exe [AllOptions] [AdditionalOptions] -- [inputs]" CommandLine=""$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]"
Outputs="[$ObjectFileName]" Outputs="[$ObjectFileName]"
FileExtensions="*.asm" FileExtensions="*.asm"
ExecutionDescription="Assembling..." ExecutionDescription="Assembling..." >
>
<Properties> <Properties>
<StringProperty <StringProperty
Name="ObjectFileName" Name="ObjectFileName"

45
src/gba/GBA-arm.cpp
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@ -753,27 +753,31 @@ static void count(u32 opcode, int cond_res)
// OP Rd,Rb,Rm LSL Rs // OP Rd,Rb,Rm LSL Rs
#ifndef VALUE_LSL_REG_C #ifndef VALUE_LSL_REG_C
#define VALUE_LSL_REG_C \ #define VALUE_LSL_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ u32 shift = reg[(opcode >> 8)&15].B.B0; \
u32 rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
if (shift == 32) { \ if (shift == 32) { \
value = 0; \ value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\ C_OUT = (rm & 1 ? true : false); \
} else if (LIKELY(shift < 32)) { \ } else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \ u32 v = rm; \
C_OUT = (v >> (32 - shift)) & 1 ? true : false;\ C_OUT = (v >> (32 - shift)) & 1 ? true : false; \
value = v << shift; \ value = v << shift; \
} else { \ } else { \
value = 0; \ value = 0; \
C_OUT = false; \ C_OUT = false; \
} \ } \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} }
#endif #endif
// OP Rd,Rb,Rm LSR # // OP Rd,Rb,Rm LSR #
#ifndef VALUE_LSR_IMM_C #ifndef VALUE_LSR_IMM_C
#define VALUE_LSR_IMM_C \ #define VALUE_LSR_IMM_C \
unsigned int shift = (opcode >> 7) & 0x1F; \ u32 shift = (opcode >> 7) & 0x1F; \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
u32 v = reg[opcode & 0x0F].I; \ u32 v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
@ -787,12 +791,16 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_LSR_REG_C #ifndef VALUE_LSR_REG_C
#define VALUE_LSR_REG_C \ #define VALUE_LSR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
u32 rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
if (shift == 32) { \ if (shift == 32) { \
value = 0; \ value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\ C_OUT = (rm & 0x80000000 ? true : false);\
} else if (LIKELY(shift < 32)) { \ } else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \ u32 v = rm; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false;\ C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
value = v >> shift; \ value = v >> shift; \
} else { \ } else { \
@ -800,7 +808,7 @@ static void count(u32 opcode, int cond_res)
C_OUT = false; \ C_OUT = false; \
} \ } \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} }
#endif #endif
// OP Rd,Rb,Rm ASR # // OP Rd,Rb,Rm ASR #
@ -826,13 +834,17 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ASR_REG_C #ifndef VALUE_ASR_REG_C
#define VALUE_ASR_REG_C \ #define VALUE_ASR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
u32 rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift < 32)) { \ if (LIKELY(shift < 32)) { \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
s32 v = reg[opcode & 0x0F].I; \ s32 v = rm; \
C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\ C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
value = v >> (int)shift; \ value = v >> (int)shift; \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} \ } \
} else { \ } else { \
if (reg[opcode & 0x0F].I & 0x80000000) { \ if (reg[opcode & 0x0F].I & 0x80000000) { \
@ -864,17 +876,20 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ROR_REG_C #ifndef VALUE_ROR_REG_C
#define VALUE_ROR_REG_C \ #define VALUE_ROR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
u32 rm = reg[opcode & 0x0F].I; \
if((opcode & 0x0F) == 15) { \
rm += 4; \
} \
if (LIKELY(shift & 0x1F)) { \ if (LIKELY(shift & 0x1F)) { \
u32 v = reg[opcode & 0x0F].I; \ u32 v = rm; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = ((v << (32 - shift)) | \ value = ((v << (32 - shift)) | \
(v >> shift)); \ (v >> shift)); \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
if (shift) \ if (shift) \
C_OUT = (value & 0x80000000 ? true : false);\ C_OUT = (value & 0x80000000 ? true : false);\
} }#endif
#endif
// OP Rd,Rb,# ROR # // OP Rd,Rb,# ROR #
#ifndef VALUE_IMM_C #ifndef VALUE_IMM_C
#define VALUE_IMM_C \ #define VALUE_IMM_C \