diff --git a/project/vc2008_mfc/nasm.props b/project/vc2008_mfc/nasm.props
new file mode 100644
index 00000000..6af58d3c
--- /dev/null
+++ b/project/vc2008_mfc/nasm.props
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup
+    Condition="'$(NASMBeforeTargets)' == '' and '$(NASMAfterTargets)' == '' and '$(ConfigurationType)' != 'Makefile'">
+    <NASMBeforeTargets>Midl</NASMBeforeTargets>
+    <NASMAfterTargets>CustomBuild</NASMAfterTargets>
+  </PropertyGroup>
+  <PropertyGroup>
+    <NASMDependsOn
+      Condition="'$(ConfigurationType)' != 'Makefile'">_SelectedFiles;$(NASMDependsOn)</NASMDependsOn>
+  </PropertyGroup>
+  <ItemDefinitionGroup>
+    <NASM>
+      <TreatWarningsAsErrors>False</TreatWarningsAsErrors>
+      <DisableOrphanLabelsWarning>False</DisableOrphanLabelsWarning>
+      <GenerateDebugInfo>False</GenerateDebugInfo>
+      <ObjectFileName>$(IntDir)%(Filename).obj</ObjectFileName>
+      <Optimization>0</Optimization>
+      <ObjectFileFormat>8</ObjectFileFormat>
+      <ErrorReportingFormat>1</ErrorReportingFormat>
+      <CommandLineTemplate>"$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]</CommandLineTemplate>
+      <Outputs>%(ObjectFileName)</Outputs>
+      <ExecutionDescription>Assembling...</ExecutionDescription>
+    </NASM>
+  </ItemDefinitionGroup>
+</Project>
\ No newline at end of file
diff --git a/project/vc2008_mfc/nasm.rules b/project/vc2008_mfc/nasm.rules
index d69b059c..b4472e99 100644
--- a/project/vc2008_mfc/nasm.rules
+++ b/project/vc2008_mfc/nasm.rules
@@ -7,11 +7,10 @@
 		<CustomBuildRule
 			Name="NASM"
 			DisplayName="Netwide Assembler"
-			CommandLine="$(SolutionDir)..\..\..\dependencies\nasm.exe [AllOptions] [AdditionalOptions] -- [inputs]"
+			CommandLine=""$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]"
 			Outputs="[$ObjectFileName]"
 			FileExtensions="*.asm"
-			ExecutionDescription="Assembling..."
-			>
+			ExecutionDescription="Assembling..."			>
 			<Properties>
 				<StringProperty
 					Name="ObjectFileName"
diff --git a/src/gba/GBA-arm.cpp b/src/gba/GBA-arm.cpp
index 2f428dae..549594f4 100644
--- a/src/gba/GBA-arm.cpp
+++ b/src/gba/GBA-arm.cpp
@@ -753,27 +753,31 @@ static void count(u32 opcode, int cond_res)
 // OP Rd,Rb,Rm LSL Rs
 #ifndef VALUE_LSL_REG_C
  #define VALUE_LSL_REG_C \
-    unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
-    if (LIKELY(shift)) {                                \
-        if (shift == 32) {                              \
-            value = 0;                                  \
-            C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\
-        } else if (LIKELY(shift < 32)) {                \
-            u32 v = reg[opcode & 0x0F].I;               \
-            C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
-            value = v << shift;                         \
-        } else {                                        \
-            value = 0;                                  \
-            C_OUT = false;                              \
-        }                                               \
-    } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+    u32 shift = reg[(opcode >> 8)&15].B.B0;                  \
+	u32 rm = reg[opcode & 0x0F].I;                           \
+	if((opcode & 0x0F) == 15) {                              \
+		rm += 4;                                             \
+	}                                                        \
+    if (LIKELY(shift)) {                                     \
+        if (shift == 32) {                                   \
+            value = 0;                                       \
+            C_OUT = (rm & 1 ? true : false);                 \
+        } else if (LIKELY(shift < 32)) {                     \
+            u32 v = rm;                                      \
+            C_OUT = (v >> (32 - shift)) & 1 ? true : false;  \
+            value = v << shift;                              \
+        } else {                                             \
+            value = 0;                                       \
+            C_OUT = false;                                   \
+        }                                                    \
+    } else {                                                 \
+        value = rm;                                          \
     }
 #endif
 // OP Rd,Rb,Rm LSR #
 #ifndef VALUE_LSR_IMM_C
  #define VALUE_LSR_IMM_C \
-    unsigned int shift = (opcode >> 7) & 0x1F;          \
+    u32 shift = (opcode >> 7) & 0x1F;                   \
     if (LIKELY(shift)) {                                \
         u32 v = reg[opcode & 0x0F].I;                   \
         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \
@@ -787,12 +791,16 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_LSR_REG_C
  #define VALUE_LSR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	u32 rm = reg[opcode & 0x0F].I;                      \
+	if((opcode & 0x0F) == 15) {                         \
+	rm += 4;                                            \
+	}                                                   \
     if (LIKELY(shift)) {                                \
         if (shift == 32) {                              \
             value = 0;                                  \
-            C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\
+            C_OUT = (rm & 0x80000000 ? true : false);\
         } else if (LIKELY(shift < 32)) {                \
-            u32 v = reg[opcode & 0x0F].I;               \
+            u32 v = rm;               \
             C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
             value = v >> shift;                         \
         } else {                                        \
@@ -800,7 +808,7 @@ static void count(u32 opcode, int cond_res)
             C_OUT = false;                              \
         }                                               \
     } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+        value = rm;                   \
     }
 #endif
 // OP Rd,Rb,Rm ASR #
@@ -826,13 +834,17 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_ASR_REG_C
  #define VALUE_ASR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	u32 rm = reg[opcode & 0x0F].I;                      \
+	if((opcode & 0x0F) == 15) {                         \
+	rm += 4;                                            \
+	}                                                   \
     if (LIKELY(shift < 32)) {                           \
         if (LIKELY(shift)) {                            \
-            s32 v = reg[opcode & 0x0F].I;               \
+            s32 v = rm;               \
             C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
             value = v >> (int)shift;                    \
         } else {                                        \
-            value = reg[opcode & 0x0F].I;               \
+            value = rm;               \
         }                                               \
     } else {                                            \
         if (reg[opcode & 0x0F].I & 0x80000000) {        \
@@ -864,17 +876,20 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_ROR_REG_C
  #define VALUE_ROR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	u32 rm = reg[opcode & 0x0F].I;                      \
+	if((opcode & 0x0F) == 15) {                         \
+	rm += 4;                                            \
+	}                                                   \
     if (LIKELY(shift & 0x1F)) {                         \
-        u32 v = reg[opcode & 0x0F].I;                   \
+        u32 v = rm;                   \
         C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \
         value = ((v << (32 - shift)) |                  \
                  (v >> shift));                         \
     } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+        value = rm;                   \
         if (shift)                                      \
             C_OUT = (value & 0x80000000 ? true : false);\
-    }
-#endif
+    }#endif
 // OP Rd,Rb,# ROR #
 #ifndef VALUE_IMM_C
  #define VALUE_IMM_C \