Hopefully this marks a return to Stella development, as I haven't had
much free time over the past month or so.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2194 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
Added infrastructure to System and Device classes to deal with CodeAccessBase
even when the bankswitching scheme bypasses the normal System::PageAccess
way of reading ROM space. This allows bankswitching schemes 2E, AR, FE and
4A50 to support emulation core 'hints' for more accurate disassembly. The
only scheme not supported now is MC, which isn't really working anyway (I've
never actually had a test ROM for this scheme).
It's getting close, folks ...
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2184 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
multiple concatentation of strings. This should be faster, or at least
lead to less string constructor calls.
Output of 'ROW' directives in the disassembly now shows only 8 items per
line, instead of 16. This allows to see all the bytes without having a
'...' in between. A future release may customize this to the size of the
output area.
Fixed output from debugger 'disasm' command to properly align different
directive types and show GFX and PGFX output.
Bumped state file version to 3.3 final, since there are no further
changes to the code that will break the file format.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2183 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
Removed reference to disassembly 'SKIP' command, since it isn't implemented
yet.
Decided on Nov. 15 for the 3.3 release date, and updated all relevant files.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2181 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
disassembly. This allows the debugger 'jump' command to be more accurate.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2180 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
for these opcodes.
The 'data source' in the debugger CPU area now also shows the SP register,
since it's used for TSX and TXS.
Bumped version # for another test release.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2177 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
Still TODO is add support for PHA, PHP, PLA and PLP, and to somehow track
accesses that are stored in zero-page RAM first. These latter items may
end up being pushed after the 3.3 release.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2175 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
(ie, each bit now takes priority over ones with lower value). This
doesn't change the processing in any way, but simply makes the bitstring
more accurately reflect what's going on.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2174 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
tired of doing it manually every time it changes.
Tweaked the handling of JSR, RTI and RTS commands, so they don't erroneously
mark associated addresses as CODE when in fact they're never actually
executed.
Several parts of the Distella code were marking areas as DATA, even though
it depending on knowing the values for the X and Y registers (which it
doesn't, as it's a static analysis). As such, these areas are now marked
as ROW instead, since that's as precise as a static analysis can do. The
processing blocks are left there, though, in case Distella is improved in
a future release.
All the above changes allow for better disassembly with less
'false positives' (ie, areas marked as CODE or DATA when they really aren't).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2172 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
emulation core, and distella). This allows to better see exactly how an
address is marked in the disassembly.
Updated Changelog with changes I forgot that I made (you know it's time
for a new release when you forget what's been added since the last one).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2170 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
the given screen. This is allowed in windowed mode, since the window
manager normally takes care of it. In the case of fullscreen mode, however,
it is never allowed, and an error message is shown.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2169 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
to use curly braces {} instead of apostrophes. This matches the
functionality from older releases.
Fixed debugger prompt messages to show correct info when opening
various files (config files, autoexec, etc).
The debugger 'type' command now accepts a range of values.
Reverted handling of ROMs that aren't in the internal database;
they're inserted with their extension again, just as in older
releases.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2168 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
weren't being flipped after a refresh. This could be the cause of a
recently reported problem with fullscreen OpenGL mode 'bleed-through'
of the desktop.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2165 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
in the emulation core, since at that point it's unknown what they are.
I suspect there are other places in the core where this is being done,
so I need to go over the entire M6502.m4 file again.
In Distella, when tentatively marking an address range as CODE, stop
when encountering the first address marked as DATA/GFX/PGFX by the
emulation core. This is required since Distella will happily disassemble
CODE as far as possible, but addresses specifically marked as
DATA/GFX/PGFX obviously indicate the CODE range is finished. This is
also why it's so important to correctly mark areas as DATA; the
Distella algorithm depends on accurate information to know when to stop.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2163 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
in a consistent way. Directives set manually have top priority, then the
results from a dynamic analysis (aka, from actually running the code), and
finally from a static analysis (aka, Distella itself).
Sometimes Distella will mark a section as CODE even if it hasn't been
marked as such dynamically. This occurs after a relative branch, which
Distella has no idea how to evaluate. It's possible that the code will
be executed eventually, but also that it will never be executed. As such,
these lines are marked with a '*', indicating that disassembly results
are tentative. If you get weird looking disassembly for these addresses,
it's probably a hint that it isn't really code at all.
PC addresses in the disassembly labels are now aligned with labels, and
shown in a lighter color. These can still be toggled on and off.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2162 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
to the emulation core. That is, if something is determined to be CODE in
Distella and *not* in the emulation core, then it shouldn't be marked as such.
Note that the disassembly will still show it as CODE; it's just that the core
will not. This fixes issues with manually specifying directives from the
debugger prompt, whereby setting a directive and later turning it off never
actually turns it off (as it was being permanently set).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2160 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
whether or not they're in cart space (aka, above $1000). Other parts of
the code can then choose whether to use them, if desired. This fixes a bug
in the 'Data src' output in the CPU area of the debugger, whereby addresses
were zeroed if they resulted from addresses below $1000.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2158 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
detection and marking of those areas into the TIA class itself, specifically
at the location of the write. In other words, there's no longer an IF
statement executed for every STx opcode; the marking is done directly
within the write to GRPx or PFx, so extra code is only executed when
actually storing to those locations.
Fixed several cases of opcodes marking an area as CODE when it should have
been DATA.
Added output to the CPU area of the debugger for displaying the source
address for loading data into the A/X/Y registers. Note that these are
only modified when actual addresses are used, so immediate and zero-page
mode will show addresses as zero (meaning that no address was involved
in retrieving the data).
Tweaked console font to better diffentiate the disassembly output between
graphics for players and graphics for the playfield.
Bumped state file format because of changes to M6502. This means old
state files will be broken.
Bumped version # for next test release.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2157 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
previously defined GFX directive is now used for player graphics
only). The 6502 core tracks each of these separately, which provides
for more accurate disassembly.
Modified debugger font and disassembler to show GFX and PGFX with
special characters, instead of using 'X' as Distella does. This also
allows gives much more informative disassembled outout.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2156 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
the various header files. Basically, I'm following advice from
Effective C++, and including only what's absolutely necessary. For
definitions that don't need to be included, the designation 'class xxx'
is used instead. This could potentially lead to faster compile times.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2155 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
marking them as GFX. Still TODO is somehow differentiate these (based
on block, colour, etc). Also requires testing to see if this slows
down the emulation too much.
Removed un-implemented debugger console commands to query the last
addresses used in the A/X/Y registers, since they're going to be added
to the debugger UI itself in the CPU area.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2153 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
values instead of 16-bit.
Fixed compilation of System class and M6502 disassembly tracking when
compiling without debugger support. In this case, the tracking is not
done, and all related operations are completely #ifdef'ed out (resulting
in no extra speed/memory usage at all).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2152 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
currently done by remembering the addresses accessed on execution of
LDA/LDX/LDY, and marking them as GFX during a zero-page STA/STX/STY.
This is obviously as WIP and required much more testing, but I'm
pleasantly surprised by how useful it is so far.
Bumped version # for AtariAge test release.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2147 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
used as a peek operand). Still TODO is deal with poke areas, which would
be relevant in carts with extended RAM.
The interaction between the internal tracking and Distella is now much
tighter, in that knowledge gained by Distella is used in the core code,
and vice versa. This allows the best of both worlds, where the internal
tracking finds stuff at runtime (that couldn't be found in a static
analysis), and Distella tracks potential paths (that haven't occurred at
runtime yet).
Added 'type' debugger prompt command, which basically queries an address
for its disassembly type (CODE/GFX/DATA, etc).
Added debugger commands to query the last address used in an operation
for various registers, but they're only stubs at the moment.
Updated the bankswitch schemes to deal with accesses in and around the
hotspot areas. Previously, peek accesses in these areas weren't being
recorded as DATA areas.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2145 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
realized that not all things that are referenced are actually data; code can be
referenced too.
Implemented handling of 'DATA' directive. This is very similar to 'GFX',
except X's are not shown for the bits, and the disassembled bytes are always
in hex. For now, it can only be activated manually with a cfg command.
Its real value will become apparent once the emulation tracks when
addresses are actually accessed, differentiating from addresses that are
never referenced (ie, 'ROW'). This will fix the current deficiency in
modifying DATA values (it can't be done, since they're packed into 16 bytes per
line and not changable).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2144 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
in general) into the emulation core. For now, this means integrating the
directive names into CartDebug, and having Distella using those same names.
The new directive names were determined by discussion with Omegamatrix on
AtariAge, and are listed in order of decreasing hierarchy:
SKIP (the 'bit' trick to skip over sections of code)
CODE (addresses accessible to the program counter)
GFX (addresses where data is loaded into TIA GRPx registers)
DATA (addresses referenced somewhere in the ROM)
ROW (addresses never referenced at all)
The next TODO item is to have the 6502 core set these values during emulation.
This is currently (crudely) done with a true/false setting in System::peek,
where true corresponds to CODE. This will be extended, so that false
corresponds to DATA. Eventually GFX will also be detected, by watching writes
to the TIA GRPx registers. Still to work out is how to detect SKIP sections.
Anything not marked with one of the above directives will be marked as ROW,
which essentially means ROM space that is never used. This will have the
nice side effect of detecting dead ROM space, potentially leading to space
optimizations.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2143 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
view. Instead of showing each separate item (in related items), simply
show a 'toggle' option instead.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2142 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
accept a second argument, indicating a range is to be used.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2141 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
stephena